xiaomi-sm8450/android_kernel_xiaomi_sm8450
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Merge branches 'clk-match-string', 'clk-ingenic', 'clk-si544-round-fix' and 'clk-bcm-stingray' into clk-next

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* clk-match-string:
  clk: use match_string() helper
  clk: bcm2835: use match_string() helper

* clk-ingenic:
  clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
  clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock
  clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle
  clk: ingenic: jz4770: Change OTG from custom to standard gated clock
  clk: ingenic: Support specifying "wait for clock stable" delay
  clk: ingenic: Add support for clocks whose gate bit is inverted

* clk-si544-round-fix:
  clk-si544: Properly round requested frequency to nearest match

* clk-bcm-stingray:
  clk: bcm: Update and add Stingray clock entries
  dt-bindings: clk: Update Stingray binding doc
This commit is contained in:
Stephen Boyd
2018-06-04 12:32:33 -07:00
parent ef1ae47094 d6347445c4 6ee3d385c2 4d3f36c5e9 5afa881c66
commit 36851edd7e
9 changed files with 179 additions and 89 deletions
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24
include/dt-bindings/clock/bcm-sr.h
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@@ -35,7 +35,7 @@
/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
#define BCM_SR_GENPLL0 0
#define BCM_SR_GENPLL0_SATA_CLK 1
#define BCM_SR_GENPLL0_125M_CLK 1
#define BCM_SR_GENPLL0_SCR_CLK 2
#define BCM_SR_GENPLL0_250M_CLK 3
#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
@@ -50,9 +50,11 @@
/* GENPLL 2 clock channel ID NITRO MHB*/
#define BCM_SR_GENPLL2 0
#define BCM_SR_GENPLL2_NIC_CLK 1
#define BCM_SR_GENPLL2_250_NITRO_CLK 2
#define BCM_SR_GENPLL2_TS_500_CLK 2
#define BCM_SR_GENPLL2_125_NITRO_CLK 3
#define BCM_SR_GENPLL2_CHIMP_CLK 4
#define BCM_SR_GENPLL2_NIC_FLASH_CLK 5
#define BCM_SR_GENPLL2_FS4_CLK 6
/* GENPLL 3 HSLS clock channel ID */
#define BCM_SR_GENPLL3 0
@@ -62,11 +64,16 @@
/* GENPLL 4 SCR clock channel ID */
#define BCM_SR_GENPLL4 0
#define BCM_SR_GENPLL4_CCN_CLK 1
#define BCM_SR_GENPLL4_TPIU_PLL_CLK 2
#define BCM_SR_GENPLL4_NOC_CLK 3
#define BCM_SR_GENPLL4_CHCLK_FS4_CLK 4
#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5
/* GENPLL 5 FS4 clock channel ID */
#define BCM_SR_GENPLL5 0
#define BCM_SR_GENPLL5_FS_CLK 1
#define BCM_SR_GENPLL5_SPU_CLK 2
#define BCM_SR_GENPLL5_FS4_HF_CLK 1
#define BCM_SR_GENPLL5_CRYPTO_AE_CLK 2
#define BCM_SR_GENPLL5_RAID_AE_CLK 3
/* GENPLL 6 NITRO clock channel ID */
#define BCM_SR_GENPLL6 0
@@ -74,13 +81,16 @@
/* LCPLL0 clock channel ID */
#define BCM_SR_LCPLL0 0
#define BCM_SR_LCPLL0_SATA_REF_CLK 1
#define BCM_SR_LCPLL0_USB_REF_CLK 2
#define BCM_SR_LCPLL0_SATA_REFPN_CLK 3
#define BCM_SR_LCPLL0_SATA_REFP_CLK 1
#define BCM_SR_LCPLL0_SATA_REFN_CLK 2
#define BCM_SR_LCPLL0_SATA_350_CLK 3
#define BCM_SR_LCPLL0_SATA_500_CLK 4
/* LCPLL1 clock channel ID */
#define BCM_SR_LCPLL1 0
#define BCM_SR_LCPLL1_WAN_CLK 1
#define BCM_SR_LCPLL1_USB_REF_CLK 2
#define BCM_SR_LCPLL1_CRMU_TS_CLK 3
/* LCPLL PCIE clock channel ID */
#define BCM_SR_LCPLL_PCIE 0