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MIPS: Add hibernation support

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[Ralf: SMP support requires CPU hotplugging which MIPS currently doesn't
support.  As implemented in this patch cache and tlb flushing will also be
invoked with interrupts disabled so smp_call_function() will blow up in
charming ways.  So limit to !SMP.]

Reviewed-by: Pavel Machek <pavel@ucw.cz>
Reviewed-by: Yan Hua <yanh@lemote.com>
Reviewed-by: Arnaud Patard <apatard@mandriva.com>
Reviewed-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Wu Zhangjin <wuzj@lemote.com>
Signed-off-by: Hu Hongbing <huhb@lemote.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Wu Zhangjin
2009-06-04 20:27:10 +08:00
committed by Ralf Baechle
parent 4bb1a1089e
commit 363c55cae5
7 changed files with 143 additions and 0 deletions
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70
arch/mips/power/hibernate.S Normal file
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/*
* Hibernation support specific for mips - temporary page tables
*
* Licensed under the GPLv2
*
* Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
* Author: Hu Hongbing <huhb@lemote.com>
* Wu Zhangjin <wuzj@lemote.com>
*/
#include <asm/asm-offsets.h>
#include <asm/regdef.h>
#include <asm/asm.h>
.text
LEAF(swsusp_arch_suspend)
PTR_LA t0, saved_regs
PTR_S ra, PT_R31(t0)
PTR_S sp, PT_R29(t0)
PTR_S fp, PT_R30(t0)
PTR_S gp, PT_R28(t0)
PTR_S s0, PT_R16(t0)
PTR_S s1, PT_R17(t0)
PTR_S s2, PT_R18(t0)
PTR_S s3, PT_R19(t0)
PTR_S s4, PT_R20(t0)
PTR_S s5, PT_R21(t0)
PTR_S s6, PT_R22(t0)
PTR_S s7, PT_R23(t0)
j swsusp_save
END(swsusp_arch_suspend)
LEAF(swsusp_arch_resume)
PTR_L t0, restore_pblist
0:
PTR_L t1, PBE_ADDRESS(t0) /* source */
PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */
PTR_ADDIU t3, t1, _PAGE_SIZE
1:
REG_L t8, (t1)
REG_S t8, (t2)
PTR_ADDIU t1, t1, SZREG
PTR_ADDIU t2, t2, SZREG
bne t1, t3, 1b
PTR_L t0, PBE_NEXT(t0)
bnez t0, 0b
/* flush caches to make sure context is in memory */
PTR_L t0, __flush_cache_all
jalr t0
/* flush tlb entries */
#ifdef CONFIG_SMP
jal flush_tlb_all
#else
jal local_flush_tlb_all
#endif
PTR_LA t0, saved_regs
PTR_L ra, PT_R31(t0)
PTR_L sp, PT_R29(t0)
PTR_L fp, PT_R30(t0)
PTR_L gp, PT_R28(t0)
PTR_L s0, PT_R16(t0)
PTR_L s1, PT_R17(t0)
PTR_L s2, PT_R18(t0)
PTR_L s3, PT_R19(t0)
PTR_L s4, PT_R20(t0)
PTR_L s5, PT_R21(t0)
PTR_L s6, PT_R22(t0)
PTR_L s7, PT_R23(t0)
PTR_LI v0, 0x0
jr ra
END(swsusp_arch_resume)