Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 core platform updates from Ingo Molnar:
"The main changes are:
- Intel Atom platform updates. (Andy Shevchenko)
- modularity fixlets. (Paul Gortmaker)
- x86 platform clockevents driver updates for lguest, uv and Xen.
(Viresh Kumar)
- Microsoft Hyper-V TSC fixlet. (Vitaly Kuznetsov)"
* 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/platform: Make atom/pmc_atom.c explicitly non-modular
x86/hyperv: Mark the Hyper-V TSC as unstable
x86/xen/time: Migrate to new set-state interface
x86/uv/time: Migrate to new set-state interface
x86/lguest/timer: Migrate to new set-state interface
x86/pci/intel_mid_pci: Use proper constants for irq polarity
x86/pci/intel_mid_pci: Make intel_mid_pci_ops static
x86/pci/intel_mid_pci: Propagate actual return code
x86/pci/intel_mid_pci: Work around for IRQ0 assignment
x86/platform/iosf_mbi: Add Intel Tangier PCI id
x86/platform/iosf_mbi: Source cleanup
x86/platform/iosf_mbi: Remove NULL pointer checks for pci_dev_put()
x86/platform/iosf_mbi: Check return value of debugfs_create properly
x86/platform/iosf_mbi: Move to dedicated folder
x86/platform/intel/pmc_atom: Move the PMC-Atom code to arch/x86/platform/atom
x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface
x86/platform/intel/pmc_atom: Supply register mappings via PMC object
x86/platform/intel/pmc_atom: Print index of device in loop
x86/platform/intel/pmc_atom: Export accessors to PMC registers
This commit is contained in:
Linus Torvalds
@@ -5,6 +5,7 @@ obj-y += efi/
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obj-y += geode/
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obj-y += goldfish/
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obj-y += iris/
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obj-y += intel/
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obj-y += intel-mid/
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obj-y += intel-quark/
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obj-y += olpc/
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@@ -1 +1,2 @@
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obj-$(CONFIG_PUNIT_ATOM_DEBUG) += punit_atom_debug.o
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obj-$(CONFIG_PMC_ATOM) += pmc_atom.o
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obj-$(CONFIG_PUNIT_ATOM_DEBUG) += punit_atom_debug.o
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460
arch/x86/platform/atom/pmc_atom.c
Normal file
460
arch/x86/platform/atom/pmc_atom.c
Normal file
@@ -0,0 +1,460 @@
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/*
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* Intel Atom SOC Power Management Controller Driver
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* Copyright (c) 2014, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/device.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <linux/io.h>
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#include <asm/pmc_atom.h>
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struct pmc_bit_map {
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const char *name;
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u32 bit_mask;
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};
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struct pmc_reg_map {
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const struct pmc_bit_map *d3_sts_0;
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const struct pmc_bit_map *d3_sts_1;
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const struct pmc_bit_map *func_dis;
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const struct pmc_bit_map *func_dis_2;
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const struct pmc_bit_map *pss;
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};
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struct pmc_dev {
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u32 base_addr;
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void __iomem *regmap;
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const struct pmc_reg_map *map;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *dbgfs_dir;
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#endif /* CONFIG_DEBUG_FS */
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bool init;
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};
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static struct pmc_dev pmc_device;
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static u32 acpi_base_addr;
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static const struct pmc_bit_map d3_sts_0_map[] = {
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{"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
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{"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
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{"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
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{"LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
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{"LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
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{"LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
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{"LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
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{"LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
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{"SCC_EMMC", BIT_SCC_EMMC},
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{"SCC_SDIO", BIT_SCC_SDIO},
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{"SCC_SDCARD", BIT_SCC_SDCARD},
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{"SCC_MIPI", BIT_SCC_MIPI},
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{"HDA", BIT_HDA},
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{"LPE", BIT_LPE},
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{"OTG", BIT_OTG},
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{"USH", BIT_USH},
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{"GBE", BIT_GBE},
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{"SATA", BIT_SATA},
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{"USB_EHCI", BIT_USB_EHCI},
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{"SEC", BIT_SEC},
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{"PCIE_PORT0", BIT_PCIE_PORT0},
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{"PCIE_PORT1", BIT_PCIE_PORT1},
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{"PCIE_PORT2", BIT_PCIE_PORT2},
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{"PCIE_PORT3", BIT_PCIE_PORT3},
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{"LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
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{"LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
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{"LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
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{"LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
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{"LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
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{"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
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{"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
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{"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
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{},
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};
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static struct pmc_bit_map byt_d3_sts_1_map[] = {
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{"SMB", BIT_SMB},
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{"OTG_SS_PHY", BIT_OTG_SS_PHY},
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{"USH_SS_PHY", BIT_USH_SS_PHY},
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{"DFX", BIT_DFX},
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{},
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};
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static struct pmc_bit_map cht_d3_sts_1_map[] = {
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{"SMB", BIT_SMB},
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{"GMM", BIT_STS_GMM},
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{"ISH", BIT_STS_ISH},
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{},
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};
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static struct pmc_bit_map cht_func_dis_2_map[] = {
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{"SMB", BIT_SMB},
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{"GMM", BIT_FD_GMM},
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{"ISH", BIT_FD_ISH},
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{},
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};
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static const struct pmc_bit_map byt_pss_map[] = {
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{"GBE", PMC_PSS_BIT_GBE},
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{"SATA", PMC_PSS_BIT_SATA},
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{"HDA", PMC_PSS_BIT_HDA},
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{"SEC", PMC_PSS_BIT_SEC},
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{"PCIE", PMC_PSS_BIT_PCIE},
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{"LPSS", PMC_PSS_BIT_LPSS},
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{"LPE", PMC_PSS_BIT_LPE},
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{"DFX", PMC_PSS_BIT_DFX},
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{"USH_CTRL", PMC_PSS_BIT_USH_CTRL},
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{"USH_SUS", PMC_PSS_BIT_USH_SUS},
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{"USH_VCCS", PMC_PSS_BIT_USH_VCCS},
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{"USH_VCCA", PMC_PSS_BIT_USH_VCCA},
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{"OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
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{"OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
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{"OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
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{"OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
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{"USB", PMC_PSS_BIT_USB},
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{"USB_SUS", PMC_PSS_BIT_USB_SUS},
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{},
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};
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static const struct pmc_bit_map cht_pss_map[] = {
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{"SATA", PMC_PSS_BIT_SATA},
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{"HDA", PMC_PSS_BIT_HDA},
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{"SEC", PMC_PSS_BIT_SEC},
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{"PCIE", PMC_PSS_BIT_PCIE},
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{"LPSS", PMC_PSS_BIT_LPSS},
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{"LPE", PMC_PSS_BIT_LPE},
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{"UFS", PMC_PSS_BIT_CHT_UFS},
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{"UXD", PMC_PSS_BIT_CHT_UXD},
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{"UXD_FD", PMC_PSS_BIT_CHT_UXD_FD},
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{"UX_ENG", PMC_PSS_BIT_CHT_UX_ENG},
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{"USB_SUS", PMC_PSS_BIT_CHT_USB_SUS},
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{"GMM", PMC_PSS_BIT_CHT_GMM},
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{"ISH", PMC_PSS_BIT_CHT_ISH},
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{"DFX_MASTER", PMC_PSS_BIT_CHT_DFX_MASTER},
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{"DFX_CLUSTER1", PMC_PSS_BIT_CHT_DFX_CLUSTER1},
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{"DFX_CLUSTER2", PMC_PSS_BIT_CHT_DFX_CLUSTER2},
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{"DFX_CLUSTER3", PMC_PSS_BIT_CHT_DFX_CLUSTER3},
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{"DFX_CLUSTER4", PMC_PSS_BIT_CHT_DFX_CLUSTER4},
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{"DFX_CLUSTER5", PMC_PSS_BIT_CHT_DFX_CLUSTER5},
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{},
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};
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static const struct pmc_reg_map byt_reg_map = {
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.d3_sts_0 = d3_sts_0_map,
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.d3_sts_1 = byt_d3_sts_1_map,
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.func_dis = d3_sts_0_map,
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.func_dis_2 = byt_d3_sts_1_map,
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.pss = byt_pss_map,
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};
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static const struct pmc_reg_map cht_reg_map = {
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.d3_sts_0 = d3_sts_0_map,
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.d3_sts_1 = cht_d3_sts_1_map,
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.func_dis = d3_sts_0_map,
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.func_dis_2 = cht_func_dis_2_map,
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.pss = cht_pss_map,
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};
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static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
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{
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return readl(pmc->regmap + reg_offset);
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}
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static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
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{
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writel(val, pmc->regmap + reg_offset);
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}
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int pmc_atom_read(int offset, u32 *value)
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{
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struct pmc_dev *pmc = &pmc_device;
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if (!pmc->init)
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return -ENODEV;
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*value = pmc_reg_read(pmc, offset);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pmc_atom_read);
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int pmc_atom_write(int offset, u32 value)
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{
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struct pmc_dev *pmc = &pmc_device;
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if (!pmc->init)
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return -ENODEV;
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pmc_reg_write(pmc, offset, value);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pmc_atom_write);
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static void pmc_power_off(void)
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{
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u16 pm1_cnt_port;
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u32 pm1_cnt_value;
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pr_info("Preparing to enter system sleep state S5\n");
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pm1_cnt_port = acpi_base_addr + PM1_CNT;
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pm1_cnt_value = inl(pm1_cnt_port);
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pm1_cnt_value &= SLEEP_TYPE_MASK;
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pm1_cnt_value |= SLEEP_TYPE_S5;
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pm1_cnt_value |= SLEEP_ENABLE;
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outl(pm1_cnt_value, pm1_cnt_port);
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}
|
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|
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static void pmc_hw_reg_setup(struct pmc_dev *pmc)
|
||||
{
|
||||
/*
|
||||
* Disable PMC S0IX_WAKE_EN events coming from:
|
||||
* - LPC clock run
|
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* - GPIO_SUS ored dedicated IRQs
|
||||
* - GPIO_SCORE ored dedicated IRQs
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* - GPIO_SUS shared IRQ
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* - GPIO_SCORE shared IRQ
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*/
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pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
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}
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#ifdef CONFIG_DEBUG_FS
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static void pmc_dev_state_print(struct seq_file *s, int reg_index,
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u32 sts, const struct pmc_bit_map *sts_map,
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u32 fd, const struct pmc_bit_map *fd_map)
|
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{
|
||||
int offset = PMC_REG_BIT_WIDTH * reg_index;
|
||||
int index;
|
||||
|
||||
for (index = 0; sts_map[index].name; index++) {
|
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seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
|
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offset + index, sts_map[index].name,
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||||
fd_map[index].bit_mask & fd ? "Disabled" : "Enabled ",
|
||||
sts_map[index].bit_mask & sts ? "D3" : "D0");
|
||||
}
|
||||
}
|
||||
|
||||
static int pmc_dev_state_show(struct seq_file *s, void *unused)
|
||||
{
|
||||
struct pmc_dev *pmc = s->private;
|
||||
const struct pmc_reg_map *m = pmc->map;
|
||||
u32 func_dis, func_dis_2;
|
||||
u32 d3_sts_0, d3_sts_1;
|
||||
|
||||
func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
|
||||
func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
|
||||
d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
|
||||
d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
|
||||
|
||||
/* Low part */
|
||||
pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
|
||||
|
||||
/* High part */
|
||||
pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pmc_dev_state_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, pmc_dev_state_show, inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations pmc_dev_state_ops = {
|
||||
.open = pmc_dev_state_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static int pmc_pss_state_show(struct seq_file *s, void *unused)
|
||||
{
|
||||
struct pmc_dev *pmc = s->private;
|
||||
const struct pmc_bit_map *map = pmc->map->pss;
|
||||
u32 pss = pmc_reg_read(pmc, PMC_PSS);
|
||||
int index;
|
||||
|
||||
for (index = 0; map[index].name; index++) {
|
||||
seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
|
||||
index, map[index].name,
|
||||
map[index].bit_mask & pss ? "Off" : "On");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pmc_pss_state_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, pmc_pss_state_show, inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations pmc_pss_state_ops = {
|
||||
.open = pmc_pss_state_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
|
||||
{
|
||||
struct pmc_dev *pmc = s->private;
|
||||
u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
|
||||
|
||||
s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
|
||||
s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
|
||||
s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
|
||||
s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
|
||||
s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
|
||||
|
||||
seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
|
||||
seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
|
||||
seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
|
||||
seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
|
||||
seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pmc_sleep_tmr_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, pmc_sleep_tmr_show, inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations pmc_sleep_tmr_ops = {
|
||||
.open = pmc_sleep_tmr_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
|
||||
{
|
||||
debugfs_remove_recursive(pmc->dbgfs_dir);
|
||||
}
|
||||
|
||||
static int pmc_dbgfs_register(struct pmc_dev *pmc)
|
||||
{
|
||||
struct dentry *dir, *f;
|
||||
|
||||
dir = debugfs_create_dir("pmc_atom", NULL);
|
||||
if (!dir)
|
||||
return -ENOMEM;
|
||||
|
||||
pmc->dbgfs_dir = dir;
|
||||
|
||||
f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
|
||||
dir, pmc, &pmc_dev_state_ops);
|
||||
if (!f)
|
||||
goto err;
|
||||
|
||||
f = debugfs_create_file("pss_state", S_IFREG | S_IRUGO,
|
||||
dir, pmc, &pmc_pss_state_ops);
|
||||
if (!f)
|
||||
goto err;
|
||||
|
||||
f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
|
||||
dir, pmc, &pmc_sleep_tmr_ops);
|
||||
if (!f)
|
||||
goto err;
|
||||
|
||||
return 0;
|
||||
err:
|
||||
pmc_dbgfs_unregister(pmc);
|
||||
return -ENODEV;
|
||||
}
|
||||
#else
|
||||
static int pmc_dbgfs_register(struct pmc_dev *pmc)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_DEBUG_FS */
|
||||
|
||||
static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
struct pmc_dev *pmc = &pmc_device;
|
||||
const struct pmc_reg_map *map = (struct pmc_reg_map *)ent->driver_data;
|
||||
int ret;
|
||||
|
||||
/* Obtain ACPI base address */
|
||||
pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
|
||||
acpi_base_addr &= ACPI_BASE_ADDR_MASK;
|
||||
|
||||
/* Install power off function */
|
||||
if (acpi_base_addr != 0 && pm_power_off == NULL)
|
||||
pm_power_off = pmc_power_off;
|
||||
|
||||
pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
|
||||
pmc->base_addr &= PMC_BASE_ADDR_MASK;
|
||||
|
||||
pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN);
|
||||
if (!pmc->regmap) {
|
||||
dev_err(&pdev->dev, "error: ioremap failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
pmc->map = map;
|
||||
|
||||
/* PMC hardware registers setup */
|
||||
pmc_hw_reg_setup(pmc);
|
||||
|
||||
ret = pmc_dbgfs_register(pmc);
|
||||
if (ret)
|
||||
dev_warn(&pdev->dev, "debugfs register failed\n");
|
||||
|
||||
pmc->init = true;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Data for PCI driver interface
|
||||
*
|
||||
* used by pci_match_id() call below.
|
||||
*/
|
||||
static const struct pci_device_id pmc_pci_ids[] = {
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_reg_map },
|
||||
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_reg_map },
|
||||
{ 0, },
|
||||
};
|
||||
|
||||
static int __init pmc_atom_init(void)
|
||||
{
|
||||
struct pci_dev *pdev = NULL;
|
||||
const struct pci_device_id *ent;
|
||||
|
||||
/* We look for our device - PCU PMC
|
||||
* we assume that there is max. one device.
|
||||
*
|
||||
* We can't use plain pci_driver mechanism,
|
||||
* as the device is really a multiple function device,
|
||||
* main driver that binds to the pci_device is lpc_ich
|
||||
* and have to find & bind to the device this way.
|
||||
*/
|
||||
for_each_pci_dev(pdev) {
|
||||
ent = pci_match_id(pmc_pci_ids, pdev);
|
||||
if (ent)
|
||||
return pmc_setup_dev(pdev, ent);
|
||||
}
|
||||
/* Device not found. */
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
device_initcall(pmc_atom_init);
|
||||
|
||||
/*
|
||||
MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
|
||||
MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
*/
|
||||
1
arch/x86/platform/intel/Makefile
Normal file
1
arch/x86/platform/intel/Makefile
Normal file
@@ -0,0 +1 @@
|
||||
obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
|
||||
327
arch/x86/platform/intel/iosf_mbi.c
Normal file
327
arch/x86/platform/intel/iosf_mbi.c
Normal file
@@ -0,0 +1,327 @@
|
||||
/*
|
||||
* IOSF-SB MailBox Interface Driver
|
||||
* Copyright (c) 2013, Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*
|
||||
* The IOSF-SB is a fabric bus available on Atom based SOC's that uses a
|
||||
* mailbox interface (MBI) to communicate with mutiple devices. This
|
||||
* driver implements access to this interface for those platforms that can
|
||||
* enumerate the device using PCI.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/capability.h>
|
||||
|
||||
#include <asm/iosf_mbi.h>
|
||||
|
||||
#define PCI_DEVICE_ID_BAYTRAIL 0x0F00
|
||||
#define PCI_DEVICE_ID_BRASWELL 0x2280
|
||||
#define PCI_DEVICE_ID_QUARK_X1000 0x0958
|
||||
#define PCI_DEVICE_ID_TANGIER 0x1170
|
||||
|
||||
static struct pci_dev *mbi_pdev;
|
||||
static DEFINE_SPINLOCK(iosf_mbi_lock);
|
||||
|
||||
static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset)
|
||||
{
|
||||
return (op << 24) | (port << 16) | (offset << 8) | MBI_ENABLE;
|
||||
}
|
||||
|
||||
static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr)
|
||||
{
|
||||
int result;
|
||||
|
||||
if (!mbi_pdev)
|
||||
return -ENODEV;
|
||||
|
||||
if (mcrx) {
|
||||
result = pci_write_config_dword(mbi_pdev, MBI_MCRX_OFFSET,
|
||||
mcrx);
|
||||
if (result < 0)
|
||||
goto fail_read;
|
||||
}
|
||||
|
||||
result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr);
|
||||
if (result < 0)
|
||||
goto fail_read;
|
||||
|
||||
result = pci_read_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr);
|
||||
if (result < 0)
|
||||
goto fail_read;
|
||||
|
||||
return 0;
|
||||
|
||||
fail_read:
|
||||
dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n", result);
|
||||
return result;
|
||||
}
|
||||
|
||||
static int iosf_mbi_pci_write_mdr(u32 mcrx, u32 mcr, u32 mdr)
|
||||
{
|
||||
int result;
|
||||
|
||||
if (!mbi_pdev)
|
||||
return -ENODEV;
|
||||
|
||||
result = pci_write_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr);
|
||||
if (result < 0)
|
||||
goto fail_write;
|
||||
|
||||
if (mcrx) {
|
||||
result = pci_write_config_dword(mbi_pdev, MBI_MCRX_OFFSET,
|
||||
mcrx);
|
||||
if (result < 0)
|
||||
goto fail_write;
|
||||
}
|
||||
|
||||
result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr);
|
||||
if (result < 0)
|
||||
goto fail_write;
|
||||
|
||||
return 0;
|
||||
|
||||
fail_write:
|
||||
dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n", result);
|
||||
return result;
|
||||
}
|
||||
|
||||
int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
|
||||
{
|
||||
u32 mcr, mcrx;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
/* Access to the GFX unit is handled by GPU code */
|
||||
if (port == BT_MBI_UNIT_GFX) {
|
||||
WARN_ON(1);
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
|
||||
mcrx = offset & MBI_MASK_HI;
|
||||
|
||||
spin_lock_irqsave(&iosf_mbi_lock, flags);
|
||||
ret = iosf_mbi_pci_read_mdr(mcrx, mcr, mdr);
|
||||
spin_unlock_irqrestore(&iosf_mbi_lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(iosf_mbi_read);
|
||||
|
||||
int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
|
||||
{
|
||||
u32 mcr, mcrx;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
/* Access to the GFX unit is handled by GPU code */
|
||||
if (port == BT_MBI_UNIT_GFX) {
|
||||
WARN_ON(1);
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
|
||||
mcrx = offset & MBI_MASK_HI;
|
||||
|
||||
spin_lock_irqsave(&iosf_mbi_lock, flags);
|
||||
ret = iosf_mbi_pci_write_mdr(mcrx, mcr, mdr);
|
||||
spin_unlock_irqrestore(&iosf_mbi_lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(iosf_mbi_write);
|
||||
|
||||
int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
|
||||
{
|
||||
u32 mcr, mcrx;
|
||||
u32 value;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
/* Access to the GFX unit is handled by GPU code */
|
||||
if (port == BT_MBI_UNIT_GFX) {
|
||||
WARN_ON(1);
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
|
||||
mcrx = offset & MBI_MASK_HI;
|
||||
|
||||
spin_lock_irqsave(&iosf_mbi_lock, flags);
|
||||
|
||||
/* Read current mdr value */
|
||||
ret = iosf_mbi_pci_read_mdr(mcrx, mcr & MBI_RD_MASK, &value);
|
||||
if (ret < 0) {
|
||||
spin_unlock_irqrestore(&iosf_mbi_lock, flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Apply mask */
|
||||
value &= ~mask;
|
||||
mdr &= mask;
|
||||
value |= mdr;
|
||||
|
||||
/* Write back */
|
||||
ret = iosf_mbi_pci_write_mdr(mcrx, mcr | MBI_WR_MASK, value);
|
||||
|
||||
spin_unlock_irqrestore(&iosf_mbi_lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(iosf_mbi_modify);
|
||||
|
||||
bool iosf_mbi_available(void)
|
||||
{
|
||||
/* Mbi isn't hot-pluggable. No remove routine is provided */
|
||||
return mbi_pdev;
|
||||
}
|
||||
EXPORT_SYMBOL(iosf_mbi_available);
|
||||
|
||||
#ifdef CONFIG_IOSF_MBI_DEBUG
|
||||
static u32 dbg_mdr;
|
||||
static u32 dbg_mcr;
|
||||
static u32 dbg_mcrx;
|
||||
|
||||
static int mcr_get(void *data, u64 *val)
|
||||
{
|
||||
*val = *(u32 *)data;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mcr_set(void *data, u64 val)
|
||||
{
|
||||
u8 command = ((u32)val & 0xFF000000) >> 24,
|
||||
port = ((u32)val & 0x00FF0000) >> 16,
|
||||
offset = ((u32)val & 0x0000FF00) >> 8;
|
||||
int err;
|
||||
|
||||
*(u32 *)data = val;
|
||||
|
||||
if (!capable(CAP_SYS_RAWIO))
|
||||
return -EACCES;
|
||||
|
||||
if (command & 1u)
|
||||
err = iosf_mbi_write(port,
|
||||
command,
|
||||
dbg_mcrx | offset,
|
||||
dbg_mdr);
|
||||
else
|
||||
err = iosf_mbi_read(port,
|
||||
command,
|
||||
dbg_mcrx | offset,
|
||||
&dbg_mdr);
|
||||
|
||||
return err;
|
||||
}
|
||||
DEFINE_SIMPLE_ATTRIBUTE(iosf_mcr_fops, mcr_get, mcr_set , "%llx\n");
|
||||
|
||||
static struct dentry *iosf_dbg;
|
||||
|
||||
static void iosf_sideband_debug_init(void)
|
||||
{
|
||||
struct dentry *d;
|
||||
|
||||
iosf_dbg = debugfs_create_dir("iosf_sb", NULL);
|
||||
if (IS_ERR_OR_NULL(iosf_dbg))
|
||||
return;
|
||||
|
||||
/* mdr */
|
||||
d = debugfs_create_x32("mdr", 0660, iosf_dbg, &dbg_mdr);
|
||||
if (!d)
|
||||
goto cleanup;
|
||||
|
||||
/* mcrx */
|
||||
d = debugfs_create_x32("mcrx", 0660, iosf_dbg, &dbg_mcrx);
|
||||
if (!d)
|
||||
goto cleanup;
|
||||
|
||||
/* mcr - initiates mailbox tranaction */
|
||||
d = debugfs_create_file("mcr", 0660, iosf_dbg, &dbg_mcr, &iosf_mcr_fops);
|
||||
if (!d)
|
||||
goto cleanup;
|
||||
|
||||
return;
|
||||
|
||||
cleanup:
|
||||
debugfs_remove_recursive(d);
|
||||
}
|
||||
|
||||
static void iosf_debugfs_init(void)
|
||||
{
|
||||
iosf_sideband_debug_init();
|
||||
}
|
||||
|
||||
static void iosf_debugfs_remove(void)
|
||||
{
|
||||
debugfs_remove_recursive(iosf_dbg);
|
||||
}
|
||||
#else
|
||||
static inline void iosf_debugfs_init(void) { }
|
||||
static inline void iosf_debugfs_remove(void) { }
|
||||
#endif /* CONFIG_IOSF_MBI_DEBUG */
|
||||
|
||||
static int iosf_mbi_probe(struct pci_dev *pdev,
|
||||
const struct pci_device_id *unused)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = pci_enable_device(pdev);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "error: could not enable device\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
mbi_pdev = pci_dev_get(pdev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pci_device_id iosf_mbi_pci_ids[] = {
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BAYTRAIL) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRASWELL) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_QUARK_X1000) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_TANGIER) },
|
||||
{ 0, },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids);
|
||||
|
||||
static struct pci_driver iosf_mbi_pci_driver = {
|
||||
.name = "iosf_mbi_pci",
|
||||
.probe = iosf_mbi_probe,
|
||||
.id_table = iosf_mbi_pci_ids,
|
||||
};
|
||||
|
||||
static int __init iosf_mbi_init(void)
|
||||
{
|
||||
iosf_debugfs_init();
|
||||
|
||||
return pci_register_driver(&iosf_mbi_pci_driver);
|
||||
}
|
||||
|
||||
static void __exit iosf_mbi_exit(void)
|
||||
{
|
||||
iosf_debugfs_remove();
|
||||
|
||||
pci_unregister_driver(&iosf_mbi_pci_driver);
|
||||
pci_dev_put(mbi_pdev);
|
||||
mbi_pdev = NULL;
|
||||
}
|
||||
|
||||
module_init(iosf_mbi_init);
|
||||
module_exit(iosf_mbi_exit);
|
||||
|
||||
MODULE_AUTHOR("David E. Box <david.e.box@linux.intel.com>");
|
||||
MODULE_DESCRIPTION("IOSF Mailbox Interface accessor");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@@ -32,8 +32,7 @@
|
||||
|
||||
static cycle_t uv_read_rtc(struct clocksource *cs);
|
||||
static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
|
||||
static void uv_rtc_timer_setup(enum clock_event_mode,
|
||||
struct clock_event_device *);
|
||||
static int uv_rtc_shutdown(struct clock_event_device *evt);
|
||||
|
||||
static struct clocksource clocksource_uv = {
|
||||
.name = RTC_NAME,
|
||||
@@ -44,14 +43,14 @@ static struct clocksource clocksource_uv = {
|
||||
};
|
||||
|
||||
static struct clock_event_device clock_event_device_uv = {
|
||||
.name = RTC_NAME,
|
||||
.features = CLOCK_EVT_FEAT_ONESHOT,
|
||||
.shift = 20,
|
||||
.rating = 400,
|
||||
.irq = -1,
|
||||
.set_next_event = uv_rtc_next_event,
|
||||
.set_mode = uv_rtc_timer_setup,
|
||||
.event_handler = NULL,
|
||||
.name = RTC_NAME,
|
||||
.features = CLOCK_EVT_FEAT_ONESHOT,
|
||||
.shift = 20,
|
||||
.rating = 400,
|
||||
.irq = -1,
|
||||
.set_next_event = uv_rtc_next_event,
|
||||
.set_state_shutdown = uv_rtc_shutdown,
|
||||
.event_handler = NULL,
|
||||
};
|
||||
|
||||
static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);
|
||||
@@ -321,24 +320,14 @@ static int uv_rtc_next_event(unsigned long delta,
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup the RTC timer in oneshot mode
|
||||
* Shutdown the RTC timer
|
||||
*/
|
||||
static void uv_rtc_timer_setup(enum clock_event_mode mode,
|
||||
struct clock_event_device *evt)
|
||||
static int uv_rtc_shutdown(struct clock_event_device *evt)
|
||||
{
|
||||
int ced_cpu = cpumask_first(evt->cpumask);
|
||||
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
case CLOCK_EVT_MODE_RESUME:
|
||||
/* Nothing to do here yet */
|
||||
break;
|
||||
case CLOCK_EVT_MODE_UNUSED:
|
||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
uv_rtc_unset_timer(ced_cpu, 1);
|
||||
break;
|
||||
}
|
||||
uv_rtc_unset_timer(ced_cpu, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void uv_rtc_interrupt(void)
|
||||
|
||||
Reference in New Issue
Block a user