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drm/i915: Use an array of register tables in command parser

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For Haswell, we will want another table of registers while retaining
the large common table of whitelisted registers shared by all gen7
devices.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
[danvet: Pipe patch through sed -e 's/\<ring\>/engine/g' to make it
apply.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jordan Justen
2016-03-06 23:30:27 -08:00
committed by Daniel Vetter
parent a6573e1f54
commit 361b027bc6
2 changed files with 75 additions and 39 deletions
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13
drivers/gpu/drm/i915/intel_ringbuffer.h
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@@ -123,7 +123,7 @@ struct intel_ringbuffer {
};
struct intel_context;
struct drm_i915_reg_descriptor;
struct drm_i915_reg_table;
/*
* we use a single page to load ctx workarounds so all of these
@@ -331,15 +331,8 @@ struct intel_engine_cs {
/*
* Table of registers allowed in commands that read/write registers.
*/
const struct drm_i915_reg_descriptor *reg_table;
int reg_count;
/*
* Table of registers allowed in commands that read/write registers, but
* only from the DRM master.
*/
const struct drm_i915_reg_descriptor *master_reg_table;
int master_reg_count;
const struct drm_i915_reg_table *reg_tables;
int reg_table_count;
/*
* Returns the bitmask for the length field of the specified command.