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Merge 7f376f1917 ("Merge tag 'mtd/fixes-for-5.10-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux") into android-mainline

Browse Source 
Steps on the way to 5.10-final

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: Iaf246e292babee342e89c090dad69e12e2cb4d75
This commit is contained in:
Greg Kroah-Hartman
2020-12-12 12:19:45 +01:00
parent 67e762efc7 7f376f1917
commit 35dcb7ff81
64 changed files with 769 additions and 395 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/clk/imx/Kconfig
View File

@@ -5,8 +5,8 @@ config MXC_CLK
depends on ARCH_MXC || COMPILE_TEST
config MXC_CLK_SCU
tristate "IMX SCU clock"
depends on ARCH_MXC || COMPILE_TEST
tristate
depends on ARCH_MXC
depends on IMX_SCU && HAVE_ARM_SMCCC
config CLK_IMX1

2
drivers/clk/renesas/r9a06g032-clocks.c
View File

@@ -55,7 +55,7 @@ struct r9a06g032_clkdesc {
u16 sel, g1, r1, g2, r2;
} dual;
};
} __packed;
};
#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \
{ .gate = _clk, .reset = _rst, \

1
drivers/gpio/gpio-arizona.c
View File

@@ -192,6 +192,7 @@ static int arizona_gpio_probe(struct platform_device *pdev)
ret = devm_gpiochip_add_data(&pdev->dev, &arizona_gpio->gpio_chip,
arizona_gpio);
if (ret < 0) {
pm_runtime_disable(&pdev->dev);
dev_err(&pdev->dev, "Could not register gpiochip, %d\n",
ret);
return ret;

2
drivers/gpio/gpio-dwapb.c
View File

@@ -724,6 +724,8 @@ static int dwapb_gpio_probe(struct platform_device *pdev)
return err;
}
platform_set_drvdata(pdev, gpio);
return 0;
}

2
drivers/gpio/gpio-eic-sprd.c
View File

@@ -598,7 +598,7 @@ static int sprd_eic_probe(struct platform_device *pdev)
*/
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
if (!res)
continue;
break;
sprd_eic->base[i] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(sprd_eic->base[i]))

16
drivers/gpio/gpio-mvebu.c
View File

@@ -1197,6 +1197,13 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
/* Some MVEBU SoCs have simple PWM support for GPIO lines */
if (IS_ENABLED(CONFIG_PWM)) {
err = mvebu_pwm_probe(pdev, mvchip, id);
if (err)
return err;
}
/* Some gpio controllers do not provide irq support */
if (!have_irqs)
return 0;
@@ -1206,7 +1213,8 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
if (!mvchip->domain) {
dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
mvchip->chip.label);
return -ENODEV;
err = -ENODEV;
goto err_pwm;
}
err = irq_alloc_domain_generic_chips(
@@ -1254,14 +1262,12 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
mvchip);
}
/* Some MVEBU SoCs have simple PWM support for GPIO lines */
if (IS_ENABLED(CONFIG_PWM))
return mvebu_pwm_probe(pdev, mvchip, id);
return 0;
err_domain:
irq_domain_remove(mvchip->domain);
err_pwm:
pwmchip_remove(&mvchip->mvpwm->chip);
return err;
}

4
drivers/gpio/gpio-zynq.c
View File

@@ -574,7 +574,7 @@ static int zynq_gpio_irq_reqres(struct irq_data *d)
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
int ret;
ret = pm_runtime_get_sync(chip->parent);
ret = pm_runtime_resume_and_get(chip->parent);
if (ret < 0)
return ret;
@@ -942,7 +942,7 @@ static int zynq_gpio_probe(struct platform_device *pdev)
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
ret = pm_runtime_get_sync(&pdev->dev);
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret < 0)
goto err_pm_dis;

5
drivers/gpio/gpiolib.c
View File

@@ -1806,6 +1806,11 @@ EXPORT_SYMBOL_GPL(gpiochip_generic_request);
*/
void gpiochip_generic_free(struct gpio_chip *gc, unsigned offset)
{
#ifdef CONFIG_PINCTRL
if (list_empty(&gc->gpiodev->pin_ranges))
return;
#endif
pinctrl_gpio_free(gc->gpiodev->base + offset);
}
EXPORT_SYMBOL_GPL(gpiochip_generic_free);

8
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
View File

@@ -459,6 +459,7 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_bo *bo;
struct amdgpu_bo_param bp;
struct drm_gem_object *gobj;
int ret;
memset(&bp, 0, sizeof(bp));
@@ -469,17 +470,20 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
bp.type = ttm_bo_type_sg;
bp.resv = resv;
dma_resv_lock(resv, NULL);
ret = amdgpu_bo_create(adev, &bp, &bo);
ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_CPU,
0, ttm_bo_type_sg, resv, &gobj);
if (ret)
goto error;
bo = gem_to_amdgpu_bo(gobj);
bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
if (dma_buf->ops != &amdgpu_dmabuf_ops)
bo->prime_shared_count = 1;
dma_resv_unlock(resv);
return &bo->tbo.base;
return gobj;
error:
dma_resv_unlock(resv);

41
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
View File

@@ -66,26 +66,12 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
bp.type = type;
bp.resv = resv;
bp.preferred_domain = initial_domain;
retry:
bp.flags = flags;
bp.domain = initial_domain;
r = amdgpu_bo_create(adev, &bp, &bo);
if (r) {
if (r != -ERESTARTSYS) {
if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
goto retry;
}
if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
goto retry;
}
DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
size, initial_domain, alignment, r);
}
if (r)
return r;
}
*obj = &bo->tbo.base;
return 0;
@@ -225,7 +211,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
uint64_t size = args->in.bo_size;
struct dma_resv *resv = NULL;
struct drm_gem_object *gobj;
uint32_t handle;
uint32_t handle, initial_domain;
int r;
/* reject invalid gem flags */
@@ -269,9 +255,28 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
resv = vm->root.base.bo->tbo.base.resv;
}
retry:
initial_domain = (u32)(0xffffffff & args->in.domains);
r = amdgpu_gem_object_create(adev, size, args->in.alignment,
(u32)(0xffffffff & args->in.domains),
initial_domain,
flags, ttm_bo_type_device, resv, &gobj);
if (r) {
if (r != -ERESTARTSYS) {
if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
goto retry;
}
if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
goto retry;
}
DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
size, initial_domain, args->in.alignment, r);
}
return r;
}
if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
if (!r) {
struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);

3
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
View File

@@ -499,6 +499,9 @@ void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev)
else
size = amdgpu_gmc_get_vbios_fb_size(adev);
if (adev->mman.keep_stolen_vga_memory)
size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION);
/* set to 0 if the pre-OS buffer uses up most of vram */
if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
size = 0;

11
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
View File

@@ -1172,7 +1172,7 @@ static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
con->dir, &con->disable_ras_err_cnt_harvest);
}
void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
struct ras_fs_if *head)
{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
@@ -1194,7 +1194,6 @@ void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
{
#if defined(CONFIG_DEBUG_FS)
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *obj;
struct ras_fs_if fs_info;
@@ -1203,7 +1202,7 @@ void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
* it won't be called in resume path, no need to check
* suspend and gpu reset status
*/
if (!con)
if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
return;
amdgpu_ras_debugfs_create_ctrl_node(adev);
@@ -1217,10 +1216,9 @@ void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
amdgpu_ras_debugfs_create(adev, &fs_info);
}
}
#endif
}
void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
static void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
struct ras_common_if *head)
{
struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
@@ -1234,7 +1232,6 @@ void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev)
{
#if defined(CONFIG_DEBUG_FS)
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *obj, *tmp;
@@ -1243,7 +1240,6 @@ static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev)
}
con->dir = NULL;
#endif
}
/* debugfs end */
@@ -1291,6 +1287,7 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
{
if (IS_ENABLED(CONFIG_DEBUG_FS))
amdgpu_ras_debugfs_remove_all(adev);
amdgpu_ras_sysfs_remove_all(adev);
return 0;

6
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
View File

@@ -607,14 +607,8 @@ int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
struct ras_common_if *head);
void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
struct ras_fs_if *head);
void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
struct ras_common_if *head);
int amdgpu_ras_error_query(struct amdgpu_device *adev,
struct ras_query_if *info);

2
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
View File

@@ -186,7 +186,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
if (err)
goto out;
err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[i]);
if (err)
goto out;
}

2
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
View File

@@ -1736,6 +1736,7 @@ static int kfd_ioctl_import_dmabuf(struct file *filep,
}
mutex_unlock(&p->mutex);
dma_buf_put(dmabuf);
args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
@@ -1745,6 +1746,7 @@ err_free:
amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL);
err_unlock:
mutex_unlock(&p->mutex);
dma_buf_put(dmabuf);
return r;
}

9
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@@ -1058,9 +1058,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
goto error;
}
/* Update the actual used number of crtc */
adev->mode_info.num_crtc = adev->dm.display_indexes_num;
/* create fake encoders for MST */
dm_dp_create_fake_mst_encoders(adev);
@@ -3251,6 +3248,10 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
enum dc_connection_type new_connection_type = dc_connection_none;
const struct dc_plane_cap *plane;
dm->display_indexes_num = dm->dc->caps.max_streams;
/* Update the actual used number of crtc */
adev->mode_info.num_crtc = adev->dm.display_indexes_num;
link_cnt = dm->dc->caps.max_links;
if (amdgpu_dm_mode_config_init(dm->adev)) {
DRM_ERROR("DM: Failed to initialize mode config\n");
@@ -3312,8 +3313,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
goto fail;
}
dm->display_indexes_num = dm->dc->caps.max_streams;
/* loops over all connectors on the board */
for (i = 0; i < link_cnt; i++) {
struct dc_link *link = NULL;

93
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
View File

@@ -579,7 +579,7 @@ static struct clk_bw_params rn_bw_params = {
};
static struct wm_table ddr4_wm_table = {
static struct wm_table ddr4_wm_table_gs = {
.entries = {
{
.wm_inst = WM_A,
@@ -616,7 +616,7 @@ static struct wm_table ddr4_wm_table = {
}
};
static struct wm_table lpddr4_wm_table = {
static struct wm_table lpddr4_wm_table_gs = {
.entries = {
{
.wm_inst = WM_A,
@@ -690,6 +690,80 @@ static struct wm_table lpddr4_wm_table_with_disabled_ppt = {
}
};
static struct wm_table ddr4_wm_table_rn = {
.entries = {
{
.wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
.sr_exit_time_us = 9.09,
.sr_enter_plus_exit_time_us = 10.14,
.valid = true,
},
{
.wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
.sr_exit_time_us = 10.12,
.sr_enter_plus_exit_time_us = 11.48,
.valid = true,
},
{
.wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
.sr_exit_time_us = 10.12,
.sr_enter_plus_exit_time_us = 11.48,
.valid = true,
},
{
.wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
.sr_exit_time_us = 10.12,
.sr_enter_plus_exit_time_us = 11.48,
.valid = true,
},
}
};
static struct wm_table lpddr4_wm_table_rn = {
.entries = {
{
.wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 7.32,
.sr_enter_plus_exit_time_us = 8.38,
.valid = true,
},
{
.wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 9.82,
.sr_enter_plus_exit_time_us = 11.196,
.valid = true,
},
{
.wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 9.89,
.sr_enter_plus_exit_time_us = 11.24,
.valid = true,
},
{
.wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 9.748,
.sr_enter_plus_exit_time_us = 11.102,
.valid = true,
},
}
};
static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
{
int i;
@@ -771,6 +845,11 @@ void rn_clk_mgr_construct(
struct dc_debug_options *debug = &ctx->dc->debug;
struct dpm_clocks clock_table = { 0 };
enum pp_smu_status status = 0;
int is_green_sardine = 0;
#if defined(CONFIG_DRM_AMD_DC_DCN)
is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev);
#endif
clk_mgr->base.ctx = ctx;
clk_mgr->base.funcs = &dcn21_funcs;
@@ -811,10 +890,16 @@ void rn_clk_mgr_construct(
if (clk_mgr->periodic_retraining_disabled) {
rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt;
} else {
rn_bw_params.wm_table = lpddr4_wm_table;
if (is_green_sardine)
rn_bw_params.wm_table = lpddr4_wm_table_gs;
else
rn_bw_params.wm_table = lpddr4_wm_table_rn;
}
} else {
rn_bw_params.wm_table = ddr4_wm_table;
if (is_green_sardine)
rn_bw_params.wm_table = ddr4_wm_table_gs;
else
rn_bw_params.wm_table = ddr4_wm_table_rn;
}
/* Saved clocks configured at boot for debug purposes */
rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);

7
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@@ -3394,10 +3394,13 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
{
uint32_t bits_per_channel = 0;
uint32_t kbps;
struct fixed31_32 link_bw_kbps;
if (timing->flags.DSC) {
kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
kbps = kbps / 160 + ((kbps % 160) ? 1 : 0);
link_bw_kbps = dc_fixpt_from_int(timing->pix_clk_100hz);
link_bw_kbps = dc_fixpt_div_int(link_bw_kbps, 160);
link_bw_kbps = dc_fixpt_mul_int(link_bw_kbps, timing->dsc_cfg.bits_per_pixel);
kbps = dc_fixpt_ceil(link_bw_kbps);
return kbps;
}

14
drivers/gpu/drm/amd/pm/inc/smu10.h
View File

@@ -136,14 +136,12 @@
#define FEATURE_CORE_CSTATES_MASK (1 << FEATURE_CORE_CSTATES_BIT)
/* Workload bits */
#define WORKLOAD_DEFAULT_BIT 0
#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
#define WORKLOAD_PPLIB_VIDEO_BIT 3
#define WORKLOAD_PPLIB_VR_BIT 4
#define WORKLOAD_PPLIB_COMPUTE_BIT 5
#define WORKLOAD_PPLIB_CUSTOM_BIT 6
#define WORKLOAD_PPLIB_COUNT 7
#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
#define WORKLOAD_PPLIB_VIDEO_BIT 2
#define WORKLOAD_PPLIB_VR_BIT 3
#define WORKLOAD_PPLIB_COMPUTE_BIT 4
#define WORKLOAD_PPLIB_CUSTOM_BIT 5
#define WORKLOAD_PPLIB_COUNT 6
typedef struct {
/* MP1_EXT_SCRATCH0 */

101
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
View File

@@ -24,6 +24,8 @@
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <drm/amdgpu_drm.h>
#include "processpptables.h"
#include <atom-types.h>
@@ -984,6 +986,8 @@ static int init_thermal_controller(
struct pp_hwmgr *hwmgr,
const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
{
struct amdgpu_device *adev = hwmgr->adev;
hwmgr->thermal_controller.ucType =
powerplay_table->sThermalController.ucType;
hwmgr->thermal_controller.ucI2cLine =
@@ -1008,7 +1012,104 @@ static int init_thermal_controller(
ATOM_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
PHM_PlatformCaps_ThermalController);
if (powerplay_table->usTableSize >= sizeof(ATOM_PPLIB_POWERPLAYTABLE3)) {
const ATOM_PPLIB_POWERPLAYTABLE3 *powerplay_table3 =
(const ATOM_PPLIB_POWERPLAYTABLE3 *)powerplay_table;
if (0 == le16_to_cpu(powerplay_table3->usFanTableOffset)) {
hwmgr->thermal_controller.use_hw_fan_control = 1;
return 0;
} else {
const ATOM_PPLIB_FANTABLE *fan_table =
(const ATOM_PPLIB_FANTABLE *)(((unsigned long)powerplay_table) +
le16_to_cpu(powerplay_table3->usFanTableOffset));
if (1 <= fan_table->ucFanTableFormat) {
hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst =
fan_table->ucTHyst;
hwmgr->thermal_controller.advanceFanControlParameters.usTMin =
le16_to_cpu(fan_table->usTMin);
hwmgr->thermal_controller.advanceFanControlParameters.usTMed =
le16_to_cpu(fan_table->usTMed);
hwmgr->thermal_controller.advanceFanControlParameters.usTHigh =
le16_to_cpu(fan_table->usTHigh);
hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
le16_to_cpu(fan_table->usPWMMin);
hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed =
le16_to_cpu(fan_table->usPWMMed);
hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh =
le16_to_cpu(fan_table->usPWMHigh);
hwmgr->thermal_controller.advanceFanControlParameters.usTMax = 10900;
hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay = 100000;
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl);
}
if (2 <= fan_table->ucFanTableFormat) {
const ATOM_PPLIB_FANTABLE2 *fan_table2 =
(const ATOM_PPLIB_FANTABLE2 *)(((unsigned long)powerplay_table) +
le16_to_cpu(powerplay_table3->usFanTableOffset));
hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
le16_to_cpu(fan_table2->usTMax);
}
if (3 <= fan_table->ucFanTableFormat) {
const ATOM_PPLIB_FANTABLE3 *fan_table3 =
(const ATOM_PPLIB_FANTABLE3 *) (((unsigned long)powerplay_table) +
le16_to_cpu(powerplay_table3->usFanTableOffset));
hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode =
fan_table3->ucFanControlMode;
if ((3 == fan_table->ucFanTableFormat) &&
(0x67B1 == adev->pdev->device))
hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM =
47;
else
hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM =
le16_to_cpu(fan_table3->usFanPWMMax);
hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity =
4836;
hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
le16_to_cpu(fan_table3->usFanOutputSensitivity);
}
if (6 <= fan_table->ucFanTableFormat) {
const ATOM_PPLIB_FANTABLE4 *fan_table4 =
(const ATOM_PPLIB_FANTABLE4 *)(((unsigned long)powerplay_table) +
le16_to_cpu(powerplay_table3->usFanTableOffset));
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_FanSpeedInTableIsRPM);
hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM =
le16_to_cpu(fan_table4->usFanRPMMax);
}
if (7 <= fan_table->ucFanTableFormat) {
const ATOM_PPLIB_FANTABLE5 *fan_table5 =
(const ATOM_PPLIB_FANTABLE5 *)(((unsigned long)powerplay_table) +
le16_to_cpu(powerplay_table3->usFanTableOffset));
if (0x67A2 == adev->pdev->device ||
0x67A9 == adev->pdev->device ||
0x67B9 == adev->pdev->device) {
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_GeminiRegulatorFanControlSupport);
hwmgr->thermal_controller.advanceFanControlParameters.usFanCurrentLow =
le16_to_cpu(fan_table5->usFanCurrentLow);
hwmgr->thermal_controller.advanceFanControlParameters.usFanCurrentHigh =
le16_to_cpu(fan_table5->usFanCurrentHigh);
hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMLow =
le16_to_cpu(fan_table5->usFanRPMLow);
hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMHigh =
le16_to_cpu(fan_table5->usFanRPMHigh);
}
}
}
}
return 0;
}

9
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
View File

@@ -1297,15 +1297,9 @@ static int conv_power_profile_to_pplib_workload(int power_profile)
int pplib_workload = 0;
switch (power_profile) {
case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
pplib_workload = WORKLOAD_DEFAULT_BIT;
break;
case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
break;
case PP_SMC_POWER_PROFILE_POWERSAVING:
pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
break;
case PP_SMC_POWER_PROFILE_VIDEO:
pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
break;
@@ -1315,6 +1309,9 @@ static int conv_power_profile_to_pplib_workload(int power_profile)
case PP_SMC_POWER_PROFILE_COMPUTE:
pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
break;
case PP_SMC_POWER_PROFILE_CUSTOM:
pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
break;
}
return pplib_workload;

2
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
View File

@@ -217,7 +217,7 @@ static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
};

2
drivers/gpu/drm/i915/display/intel_display.c
View File

@@ -18040,7 +18040,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
*/
ret = intel_initial_commit(&i915->drm);
if (ret)
return ret;
drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
intel_overlay_setup(i915);

2
drivers/gpu/drm/i915/display/intel_dp.c
View File

@@ -573,7 +573,7 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
return 0;
}
/* Also take into account max slice width */
min_slice_count = min_t(u8, min_slice_count,
min_slice_count = max_t(u8, min_slice_count,
DIV_ROUND_UP(mode_hdisplay,
max_slice_width));

7
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
View File

@@ -3097,7 +3097,7 @@ static void retire_requests(struct intel_timeline *tl, struct i915_request *end)
break;
}
static void eb_request_add(struct i915_execbuffer *eb)
static int eb_request_add(struct i915_execbuffer *eb, int err)
{
struct i915_request *rq = eb->request;
struct intel_timeline * const tl = i915_request_timeline(rq);
@@ -3118,6 +3118,7 @@ static void eb_request_add(struct i915_execbuffer *eb)
/* Serialise with context_close via the add_to_timeline */
i915_request_set_error_once(rq, -ENOENT);
__i915_request_skip(rq);
err = -ENOENT; /* override any transient errors */
}
__i915_request_queue(rq, &attr);
@@ -3127,6 +3128,8 @@ static void eb_request_add(struct i915_execbuffer *eb)
retire_requests(tl, prev);
mutex_unlock(&tl->mutex);
return err;
}
static const i915_user_extension_fn execbuf_extensions[] = {
@@ -3332,7 +3335,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
err = eb_submit(&eb, batch);
err_request:
i915_request_get(eb.request);
eb_request_add(&eb);
err = eb_request_add(&eb, err);
if (eb.fences)
signal_fence_array(&eb);

7
drivers/gpu/drm/i915/gt/intel_lrc.c
View File

@@ -2788,6 +2788,9 @@ static void __execlists_hold(struct i915_request *rq)
static bool execlists_hold(struct intel_engine_cs *engine,
struct i915_request *rq)
{
if (i915_request_on_hold(rq))
return false;
spin_lock_irq(&engine->active.lock);
if (i915_request_completed(rq)) { /* too late! */
@@ -3169,9 +3172,11 @@ static void execlists_submission_tasklet(unsigned long data)
spin_unlock_irqrestore(&engine->active.lock, flags);
/* Recheck after serialising with direct-submission */
if (unlikely(timeout && preempt_timeout(engine)))
if (unlikely(timeout && preempt_timeout(engine))) {
cancel_timer(&engine->execlists.preempt);
execlists_reset(engine, "preemption time out");
}
}
}
static void __execlists_kick(struct intel_engine_execlists *execlists)

7
drivers/gpu/drm/i915/gt/intel_mocs.c
View File

@@ -59,8 +59,7 @@ struct drm_i915_mocs_table {
#define _L3_CACHEABILITY(value) ((value) << 4)
/* Helper defines */
#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
#define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
/* (e)LLC caching options */
/*
@@ -328,11 +327,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
if (INTEL_GEN(i915) >= 12) {
table->size = ARRAY_SIZE(tgl_mocs_table);
table->table = tgl_mocs_table;
table->n_entries = GEN11_NUM_MOCS_ENTRIES;
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
} else if (IS_GEN(i915, 11)) {
table->size = ARRAY_SIZE(icl_mocs_table);
table->table = icl_mocs_table;
table->n_entries = GEN11_NUM_MOCS_ENTRIES;
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
} else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
table->size = ARRAY_SIZE(skl_mocs_table);
table->n_entries = GEN9_NUM_MOCS_ENTRIES;

2
drivers/gpu/drm/i915/gt/shmem_utils.c
View File

@@ -73,7 +73,7 @@ void *shmem_pin_map(struct file *file)
mapping_set_unevictable(file->f_mapping);
return vaddr;
err_page:
while (--i >= 0)
while (i--)
put_page(pages[i]);
kvfree(pages);
return NULL;

4
drivers/gpu/drm/i915/selftests/i915_gem.c
View File

@@ -211,8 +211,8 @@ static int igt_gem_ww_ctx(void *arg)
return PTR_ERR(obj);
obj2 = i915_gem_object_create_internal(i915, PAGE_SIZE);
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
if (IS_ERR(obj2)) {
err = PTR_ERR(obj2);
goto put1;
}

2
drivers/mmc/core/block.c
View File

@@ -580,7 +580,7 @@ static int __mmc_blk_ioctl_cmd(struct mmc_card *card, struct mmc_blk_data *md,
memcpy(&(idata->ic.response), cmd.resp, sizeof(cmd.resp));
if (idata->rpmb || (cmd.flags & MMC_RSP_R1B)) {
if (idata->rpmb || (cmd.flags & MMC_RSP_R1B) == MMC_RSP_R1B) {
/*
* Ensure RPMB/R1B command has completed by polling CMD13
* "Send Status".

39
drivers/mmc/host/mtk-sd.c
View File

@@ -446,7 +446,7 @@ struct msdc_host {
static const struct mtk_mmc_compatible mt8135_compat = {
.clk_div_bits = 8,
.recheck_sdio_irq = false,
.recheck_sdio_irq = true,
.hs400_tune = false,
.pad_tune_reg = MSDC_PAD_TUNE,
.async_fifo = false,
@@ -485,7 +485,7 @@ static const struct mtk_mmc_compatible mt8183_compat = {
static const struct mtk_mmc_compatible mt2701_compat = {
.clk_div_bits = 12,
.recheck_sdio_irq = false,
.recheck_sdio_irq = true,
.hs400_tune = false,
.pad_tune_reg = MSDC_PAD_TUNE0,
.async_fifo = true,
@@ -511,7 +511,7 @@ static const struct mtk_mmc_compatible mt2712_compat = {
static const struct mtk_mmc_compatible mt7622_compat = {
.clk_div_bits = 12,
.recheck_sdio_irq = false,
.recheck_sdio_irq = true,
.hs400_tune = false,
.pad_tune_reg = MSDC_PAD_TUNE0,
.async_fifo = true,
@@ -524,7 +524,7 @@ static const struct mtk_mmc_compatible mt7622_compat = {
static const struct mtk_mmc_compatible mt8516_compat = {
.clk_div_bits = 12,
.recheck_sdio_irq = false,
.recheck_sdio_irq = true,
.hs400_tune = false,
.pad_tune_reg = MSDC_PAD_TUNE0,
.async_fifo = true,
@@ -535,7 +535,7 @@ static const struct mtk_mmc_compatible mt8516_compat = {
static const struct mtk_mmc_compatible mt7620_compat = {
.clk_div_bits = 8,
.recheck_sdio_irq = false,
.recheck_sdio_irq = true,
.hs400_tune = false,
.pad_tune_reg = MSDC_PAD_TUNE,
.async_fifo = false,
@@ -548,6 +548,7 @@ static const struct mtk_mmc_compatible mt7620_compat = {
static const struct mtk_mmc_compatible mt6779_compat = {
.clk_div_bits = 12,
.recheck_sdio_irq = false,
.hs400_tune = false,
.pad_tune_reg = MSDC_PAD_TUNE0,
.async_fifo = true,
@@ -2603,7 +2604,6 @@ static int msdc_drv_remove(struct platform_device *pdev)
return 0;
}
#ifdef CONFIG_PM
static void msdc_save_reg(struct msdc_host *host)
{
u32 tune_reg = host->dev_comp->pad_tune_reg;
@@ -2662,7 +2662,7 @@ static void msdc_restore_reg(struct msdc_host *host)
__msdc_enable_sdio_irq(host, 1);
}
static int msdc_runtime_suspend(struct device *dev)
static int __maybe_unused msdc_runtime_suspend(struct device *dev)
{
struct mmc_host *mmc = dev_get_drvdata(dev);
struct msdc_host *host = mmc_priv(mmc);
@@ -2672,7 +2672,7 @@ static int msdc_runtime_suspend(struct device *dev)
return 0;
}
static int msdc_runtime_resume(struct device *dev)
static int __maybe_unused msdc_runtime_resume(struct device *dev)
{
struct mmc_host *mmc = dev_get_drvdata(dev);
struct msdc_host *host = mmc_priv(mmc);
@@ -2681,11 +2681,28 @@ static int msdc_runtime_resume(struct device *dev)
msdc_restore_reg(host);
return 0;
}
#endif
static int __maybe_unused msdc_suspend(struct device *dev)
{
struct mmc_host *mmc = dev_get_drvdata(dev);
int ret;
if (mmc->caps2 & MMC_CAP2_CQE) {
ret = cqhci_suspend(mmc);
if (ret)
return ret;
}
return pm_runtime_force_suspend(dev);
}
static int __maybe_unused msdc_resume(struct device *dev)
{
return pm_runtime_force_resume(dev);
}
static const struct dev_pm_ops msdc_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
};

3
drivers/mmc/host/sdhci-of-arasan.c
View File

@@ -1186,16 +1186,19 @@ static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
.soc_ctl_map = &intel_keembay_soc_ctl_map,
.pdata = &sdhci_keembay_emmc_pdata,
.clk_ops = &arasan_clk_ops,
};
static struct sdhci_arasan_of_data intel_keembay_sd_data = {
.soc_ctl_map = &intel_keembay_soc_ctl_map,
.pdata = &sdhci_keembay_sd_pdata,
.clk_ops = &arasan_clk_ops,
};
static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
.soc_ctl_map = &intel_keembay_soc_ctl_map,
.pdata = &sdhci_keembay_sdio_pdata,
.clk_ops = &arasan_clk_ops,
};
static const struct of_device_id sdhci_arasan_of_match[] = {

6
drivers/mmc/host/tmio_mmc_core.c
View File

@@ -927,9 +927,9 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
switch (ios->power_mode) {
case MMC_POWER_OFF:
tmio_mmc_power_off(host);
/* Downgrade ensures a sane state for tuning HW (e.g. SCC) */
if (host->mmc->ops->hs400_downgrade)
host->mmc->ops->hs400_downgrade(host->mmc);
/* For R-Car Gen2+, we need to reset SDHI specific SCC */
if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
host->reset(host);
host->set_clock(host, 0);
break;
case MMC_POWER_UP:

2
drivers/mtd/nand/raw/ams-delta.c
View File

@@ -218,6 +218,8 @@ static int gpio_nand_setup_interface(struct nand_chip *this, int csline,
static int gpio_nand_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;

2
drivers/mtd/nand/raw/au1550nd.c
View File

@@ -239,6 +239,8 @@ static int au1550nd_exec_op(struct nand_chip *this,
static int au1550nd_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;

2
drivers/mtd/nand/raw/gpio.c
View File

@@ -164,6 +164,8 @@ static int gpio_nand_exec_op(struct nand_chip *chip,
static int gpio_nand_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;

2
drivers/mtd/nand/raw/mpc5121_nfc.c
View File

@@ -606,6 +606,8 @@ static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
static int mpc5121_nfc_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;

2
drivers/mtd/nand/raw/orion_nand.c
View File

@@ -86,6 +86,8 @@ static void orion_nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
static int orion_nand_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;

2
drivers/mtd/nand/raw/pasemi_nand.c
View File

@@ -77,6 +77,8 @@ static int pasemi_device_ready(struct nand_chip *chip)
static int pasemi_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;

2
drivers/mtd/nand/raw/plat_nand.c
View File

@@ -22,6 +22,8 @@ struct plat_nand_data {
static int plat_nand_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;

2
drivers/mtd/nand/raw/socrates_nand.c
View File

@@ -120,6 +120,8 @@ static int socrates_nand_device_ready(struct nand_chip *nand_chip)
static int socrates_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;

2
drivers/mtd/nand/raw/xway_nand.c
View File

@@ -149,6 +149,8 @@ static void xway_write_buf(struct nand_chip *chip, const u_char *buf, int len)
static int xway_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;

74
drivers/pinctrl/aspeed/pinctrl-aspeed.c
View File

@@ -286,14 +286,76 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
static bool aspeed_expr_is_gpio(const struct aspeed_sig_expr *expr)
{
/*
* The signal type is GPIO if the signal name has "GPI" as a prefix.
* strncmp (rather than strcmp) is used to implement the prefix
* requirement.
* We need to differentiate between GPIO and non-GPIO signals to
* implement the gpio_request_enable() interface. For better or worse
* the ASPEED pinctrl driver uses the expression names to determine
* whether an expression will mux a pin for GPIO.
*
* expr->signal might look like "GPIOB1" in the GPIO case.
* expr->signal might look like "GPIT0" in the GPI case.
* Generally we have the following - A GPIO such as B1 has:
*
* - expr->signal set to "GPIOB1"
* - expr->function set to "GPIOB1"
*
* Using this fact we can determine whether the provided expression is
* a GPIO expression by testing the signal name for the string prefix
* "GPIO".
*
* However, some GPIOs are input-only, and the ASPEED datasheets name
* them differently. An input-only GPIO such as T0 has:
*
* - expr->signal set to "GPIT0"
* - expr->function set to "GPIT0"
*
* It's tempting to generalise the prefix test from "GPIO" to "GPI" to
* account for both GPIOs and GPIs, but in doing so we run aground on
* another feature:
*
* Some pins in the ASPEED BMC SoCs have a "pass-through" GPIO
* function where the input state of one pin is replicated as the
* output state of another (as if they were shorted together - a mux
* configuration that is typically enabled by hardware strapping).
* This feature allows the BMC to pass e.g. power button state through
* to the host while the BMC is yet to boot, but take control of the
* button state once the BMC has booted by muxing each pin as a
* separate, pin-specific GPIO.
*
* Conceptually this pass-through mode is a form of GPIO and is named
* as such in the datasheets, e.g. "GPID0". This naming similarity
* trips us up with the simple GPI-prefixed-signal-name scheme
* discussed above, as the pass-through configuration is not what we
* want when muxing a pin as GPIO for the GPIO subsystem.
*
* On e.g. the AST2400, a pass-through function "GPID0" is grouped on
* balls A18 and D16, where we have:
*
* For ball A18:
* - expr->signal set to "GPID0IN"
* - expr->function set to "GPID0"
*
* For ball D16:
* - expr->signal set to "GPID0OUT"
* - expr->function set to "GPID0"
*
* By contrast, the pin-specific GPIO expressions for the same pins are
* as follows:
*
* For ball A18:
* - expr->signal looks like "GPIOD0"
* - expr->function looks like "GPIOD0"
*
* For ball D16:
* - expr->signal looks like "GPIOD1"
* - expr->function looks like "GPIOD1"
*
* Testing both the signal _and_ function names gives us the means
* differentiate the pass-through GPIO pinmux configuration from the
* pin-specific configuration that the GPIO subsystem is after: An
* expression is a pin-specific (non-pass-through) GPIO configuration
* if the signal prefix is "GPI" and the signal name matches the
* function name.
*/
return strncmp(expr->signal, "GPI", 3) == 0;
return !strncmp(expr->signal, "GPI", 3) &&
!strcmp(expr->signal, expr->function);
}
static bool aspeed_gpio_in_exprs(const struct aspeed_sig_expr **exprs)

7
drivers/pinctrl/aspeed/pinmux-aspeed.h
View File

@@ -452,10 +452,11 @@ struct aspeed_sig_desc {
* evaluation of the descriptors.
*
* @signal: The signal name for the priority level on the pin. If the signal
* type is GPIO, then the signal name must begin with the string
* "GPIO", e.g. GPIOA0, GPIOT4 etc.
* type is GPIO, then the signal name must begin with the
* prefix "GPI", e.g. GPIOA0, GPIT0 etc.
* @function: The name of the function the signal participates in for the
* associated expression
* associated expression. For pin-specific GPIO, the function
* name must match the signal name.
* @ndescs: The number of signal descriptors in the expression
* @descs: Pointer to an array of signal descriptors that comprise the
* function expression

8
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@@ -1049,7 +1049,6 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
debounce = readl(db_reg);
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
if (arg)
conf |= BYT_DEBOUNCE_EN;
@@ -1058,24 +1057,31 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
switch (arg) {
case 375:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce |= BYT_DEBOUNCE_PULSE_375US;
break;
case 750:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce |= BYT_DEBOUNCE_PULSE_750US;
break;
case 1500:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce |= BYT_DEBOUNCE_PULSE_1500US;
break;
case 3000:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce |= BYT_DEBOUNCE_PULSE_3MS;
break;
case 6000:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce |= BYT_DEBOUNCE_PULSE_6MS;
break;
case 12000:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce |= BYT_DEBOUNCE_PULSE_12MS;
break;
case 24000:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce |= BYT_DEBOUNCE_PULSE_24MS;
break;
default:

4
drivers/pinctrl/intel/pinctrl-intel.c
View File

@@ -442,8 +442,8 @@ static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
value |= PADCFG0_PMODE_GPIO;
/* Disable input and output buffers */
value &= ~PADCFG0_GPIORXDIS;
value &= ~PADCFG0_GPIOTXDIS;
value |= PADCFG0_GPIORXDIS;
value |= PADCFG0_GPIOTXDIS;
/* Disable SCI/SMI/NMI generation */
value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);

452
drivers/pinctrl/intel/pinctrl-jasperlake.c
View File

@@ -16,7 +16,7 @@
#define JSL_PAD_OWN 0x020
#define JSL_PADCFGLOCK 0x080
#define JSL_HOSTSW_OWN 0x0b0
#define JSL_HOSTSW_OWN 0x0c0
#define JSL_GPI_IS 0x100
#define JSL_GPI_IE 0x120
@@ -65,252 +65,263 @@ static const struct pinctrl_pin_desc jsl_pins[] = {
PINCTRL_PIN(17, "EMMC_CLK"),
PINCTRL_PIN(18, "EMMC_RESETB"),
PINCTRL_PIN(19, "A4WP_PRESENT"),
/* SPI */
PINCTRL_PIN(20, "SPI0_IO_2"),
PINCTRL_PIN(21, "SPI0_IO_3"),
PINCTRL_PIN(22, "SPI0_MOSI_IO_0"),
PINCTRL_PIN(23, "SPI0_MISO_IO_1"),
PINCTRL_PIN(24, "SPI0_TPM_CSB"),
PINCTRL_PIN(25, "SPI0_FLASH_0_CSB"),
PINCTRL_PIN(26, "SPI0_FLASH_1_CSB"),
PINCTRL_PIN(27, "SPI0_CLK"),
PINCTRL_PIN(28, "SPI0_CLK_LOOPBK"),
/* GPP_B */
PINCTRL_PIN(20, "CORE_VID_0"),
PINCTRL_PIN(21, "CORE_VID_1"),
PINCTRL_PIN(22, "VRALERTB"),
PINCTRL_PIN(23, "CPU_GP_2"),
PINCTRL_PIN(24, "CPU_GP_3"),
PINCTRL_PIN(25, "SRCCLKREQB_0"),
PINCTRL_PIN(26, "SRCCLKREQB_1"),
PINCTRL_PIN(27, "SRCCLKREQB_2"),
PINCTRL_PIN(28, "SRCCLKREQB_3"),
PINCTRL_PIN(29, "SRCCLKREQB_4"),
PINCTRL_PIN(30, "SRCCLKREQB_5"),
PINCTRL_PIN(31, "PMCALERTB"),
PINCTRL_PIN(32, "SLP_S0B"),
PINCTRL_PIN(33, "PLTRSTB"),
PINCTRL_PIN(34, "SPKR"),
PINCTRL_PIN(35, "GSPI0_CS0B"),
PINCTRL_PIN(36, "GSPI0_CLK"),
PINCTRL_PIN(37, "GSPI0_MISO"),
PINCTRL_PIN(38, "GSPI0_MOSI"),
PINCTRL_PIN(39, "GSPI1_CS0B"),
PINCTRL_PIN(40, "GSPI1_CLK"),
PINCTRL_PIN(41, "GSPI1_MISO"),
PINCTRL_PIN(42, "GSPI1_MOSI"),
PINCTRL_PIN(43, "DDSP_HPD_A"),
PINCTRL_PIN(44, "GSPI0_CLK_LOOPBK"),
PINCTRL_PIN(45, "GSPI1_CLK_LOOPBK"),
PINCTRL_PIN(29, "CORE_VID_0"),
PINCTRL_PIN(30, "CORE_VID_1"),
PINCTRL_PIN(31, "VRALERTB"),
PINCTRL_PIN(32, "CPU_GP_2"),
PINCTRL_PIN(33, "CPU_GP_3"),
PINCTRL_PIN(34, "SRCCLKREQB_0"),
PINCTRL_PIN(35, "SRCCLKREQB_1"),
PINCTRL_PIN(36, "SRCCLKREQB_2"),
PINCTRL_PIN(37, "SRCCLKREQB_3"),
PINCTRL_PIN(38, "SRCCLKREQB_4"),
PINCTRL_PIN(39, "SRCCLKREQB_5"),
PINCTRL_PIN(40, "PMCALERTB"),
PINCTRL_PIN(41, "SLP_S0B"),
PINCTRL_PIN(42, "PLTRSTB"),
PINCTRL_PIN(43, "SPKR"),
PINCTRL_PIN(44, "GSPI0_CS0B"),
PINCTRL_PIN(45, "GSPI0_CLK"),
PINCTRL_PIN(46, "GSPI0_MISO"),
PINCTRL_PIN(47, "GSPI0_MOSI"),
PINCTRL_PIN(48, "GSPI1_CS0B"),
PINCTRL_PIN(49, "GSPI1_CLK"),
PINCTRL_PIN(50, "GSPI1_MISO"),
PINCTRL_PIN(51, "GSPI1_MOSI"),
PINCTRL_PIN(52, "DDSP_HPD_A"),
PINCTRL_PIN(53, "GSPI0_CLK_LOOPBK"),
PINCTRL_PIN(54, "GSPI1_CLK_LOOPBK"),
/* GPP_A */
PINCTRL_PIN(46, "ESPI_IO_0"),
PINCTRL_PIN(47, "ESPI_IO_1"),
PINCTRL_PIN(48, "ESPI_IO_2"),
PINCTRL_PIN(49, "ESPI_IO_3"),
PINCTRL_PIN(50, "ESPI_CSB"),
PINCTRL_PIN(51, "ESPI_CLK"),
PINCTRL_PIN(52, "ESPI_RESETB"),
PINCTRL_PIN(53, "SMBCLK"),
PINCTRL_PIN(54, "SMBDATA"),
PINCTRL_PIN(55, "SMBALERTB"),
PINCTRL_PIN(56, "CPU_GP_0"),
PINCTRL_PIN(57, "CPU_GP_1"),
PINCTRL_PIN(58, "USB2_OCB_1"),
PINCTRL_PIN(59, "USB2_OCB_2"),
PINCTRL_PIN(60, "USB2_OCB_3"),
PINCTRL_PIN(61, "DDSP_HPD_A_TIME_SYNC_0"),
PINCTRL_PIN(62, "DDSP_HPD_B"),
PINCTRL_PIN(63, "DDSP_HPD_C"),
PINCTRL_PIN(64, "USB2_OCB_0"),
PINCTRL_PIN(65, "PCHHOTB"),
PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
PINCTRL_PIN(55, "ESPI_IO_0"),
PINCTRL_PIN(56, "ESPI_IO_1"),
PINCTRL_PIN(57, "ESPI_IO_2"),
PINCTRL_PIN(58, "ESPI_IO_3"),
PINCTRL_PIN(59, "ESPI_CSB"),
PINCTRL_PIN(60, "ESPI_CLK"),
PINCTRL_PIN(61, "ESPI_RESETB"),
PINCTRL_PIN(62, "SMBCLK"),
PINCTRL_PIN(63, "SMBDATA"),
PINCTRL_PIN(64, "SMBALERTB"),
PINCTRL_PIN(65, "CPU_GP_0"),
PINCTRL_PIN(66, "CPU_GP_1"),
PINCTRL_PIN(67, "USB2_OCB_1"),
PINCTRL_PIN(68, "USB2_OCB_2"),
PINCTRL_PIN(69, "USB2_OCB_3"),
PINCTRL_PIN(70, "DDSP_HPD_A_TIME_SYNC_0"),
PINCTRL_PIN(71, "DDSP_HPD_B"),
PINCTRL_PIN(72, "DDSP_HPD_C"),
PINCTRL_PIN(73, "USB2_OCB_0"),
PINCTRL_PIN(74, "PCHHOTB"),
PINCTRL_PIN(75, "ESPI_CLK_LOOPBK"),
/* GPP_S */
PINCTRL_PIN(67, "SNDW1_CLK"),
PINCTRL_PIN(68, "SNDW1_DATA"),
PINCTRL_PIN(69, "SNDW2_CLK"),
PINCTRL_PIN(70, "SNDW2_DATA"),
PINCTRL_PIN(71, "SNDW1_CLK"),
PINCTRL_PIN(72, "SNDW1_DATA"),
PINCTRL_PIN(73, "SNDW4_CLK_DMIC_CLK_0"),
PINCTRL_PIN(74, "SNDW4_DATA_DMIC_DATA_0"),
PINCTRL_PIN(76, "SNDW1_CLK"),
PINCTRL_PIN(77, "SNDW1_DATA"),
PINCTRL_PIN(78, "SNDW2_CLK"),
PINCTRL_PIN(79, "SNDW2_DATA"),
PINCTRL_PIN(80, "SNDW1_CLK"),
PINCTRL_PIN(81, "SNDW1_DATA"),
PINCTRL_PIN(82, "SNDW4_CLK_DMIC_CLK_0"),
PINCTRL_PIN(83, "SNDW4_DATA_DMIC_DATA_0"),
/* GPP_R */
PINCTRL_PIN(75, "HDA_BCLK"),
PINCTRL_PIN(76, "HDA_SYNC"),
PINCTRL_PIN(77, "HDA_SDO"),
PINCTRL_PIN(78, "HDA_SDI_0"),
PINCTRL_PIN(79, "HDA_RSTB"),
PINCTRL_PIN(80, "HDA_SDI_1"),
PINCTRL_PIN(81, "I2S1_SFRM"),
PINCTRL_PIN(82, "I2S1_TXD"),
PINCTRL_PIN(84, "HDA_BCLK"),
PINCTRL_PIN(85, "HDA_SYNC"),
PINCTRL_PIN(86, "HDA_SDO"),
PINCTRL_PIN(87, "HDA_SDI_0"),
PINCTRL_PIN(88, "HDA_RSTB"),
PINCTRL_PIN(89, "HDA_SDI_1"),
PINCTRL_PIN(90, "I2S1_SFRM"),
PINCTRL_PIN(91, "I2S1_TXD"),
/* GPP_H */
PINCTRL_PIN(83, "GPPC_H_0"),
PINCTRL_PIN(84, "SD_PWR_EN_B"),
PINCTRL_PIN(85, "MODEM_CLKREQ"),
PINCTRL_PIN(86, "SX_EXIT_HOLDOFFB"),
PINCTRL_PIN(87, "I2C2_SDA"),
PINCTRL_PIN(88, "I2C2_SCL"),
PINCTRL_PIN(89, "I2C3_SDA"),
PINCTRL_PIN(90, "I2C3_SCL"),
PINCTRL_PIN(91, "I2C4_SDA"),
PINCTRL_PIN(92, "I2C4_SCL"),
PINCTRL_PIN(93, "CPU_VCCIO_PWR_GATEB"),
PINCTRL_PIN(94, "I2S2_SCLK"),
PINCTRL_PIN(95, "I2S2_SFRM"),
PINCTRL_PIN(96, "I2S2_TXD"),
PINCTRL_PIN(97, "I2S2_RXD"),
PINCTRL_PIN(98, "I2S1_SCLK"),
PINCTRL_PIN(99, "GPPC_H_16"),
PINCTRL_PIN(100, "GPPC_H_17"),
PINCTRL_PIN(101, "GPPC_H_18"),
PINCTRL_PIN(102, "GPPC_H_19"),
PINCTRL_PIN(103, "GPPC_H_20"),
PINCTRL_PIN(104, "GPPC_H_21"),
PINCTRL_PIN(105, "GPPC_H_22"),
PINCTRL_PIN(106, "GPPC_H_23"),
PINCTRL_PIN(92, "GPPC_H_0"),
PINCTRL_PIN(93, "SD_PWR_EN_B"),
PINCTRL_PIN(94, "MODEM_CLKREQ"),
PINCTRL_PIN(95, "SX_EXIT_HOLDOFFB"),
PINCTRL_PIN(96, "I2C2_SDA"),
PINCTRL_PIN(97, "I2C2_SCL"),
PINCTRL_PIN(98, "I2C3_SDA"),
PINCTRL_PIN(99, "I2C3_SCL"),
PINCTRL_PIN(100, "I2C4_SDA"),
PINCTRL_PIN(101, "I2C4_SCL"),
PINCTRL_PIN(102, "CPU_VCCIO_PWR_GATEB"),
PINCTRL_PIN(103, "I2S2_SCLK"),
PINCTRL_PIN(104, "I2S2_SFRM"),
PINCTRL_PIN(105, "I2S2_TXD"),
PINCTRL_PIN(106, "I2S2_RXD"),
PINCTRL_PIN(107, "I2S1_SCLK"),
PINCTRL_PIN(108, "GPPC_H_16"),
PINCTRL_PIN(109, "GPPC_H_17"),
PINCTRL_PIN(110, "GPPC_H_18"),
PINCTRL_PIN(111, "GPPC_H_19"),
PINCTRL_PIN(112, "GPPC_H_20"),
PINCTRL_PIN(113, "GPPC_H_21"),
PINCTRL_PIN(114, "GPPC_H_22"),
PINCTRL_PIN(115, "GPPC_H_23"),
/* GPP_D */
PINCTRL_PIN(107, "SPI1_CSB"),
PINCTRL_PIN(108, "SPI1_CLK"),
PINCTRL_PIN(109, "SPI1_MISO_IO_1"),
PINCTRL_PIN(110, "SPI1_MOSI_IO_0"),
PINCTRL_PIN(111, "ISH_I2C0_SDA"),
PINCTRL_PIN(112, "ISH_I2C0_SCL"),
PINCTRL_PIN(113, "ISH_I2C1_SDA"),
PINCTRL_PIN(114, "ISH_I2C1_SCL"),
PINCTRL_PIN(115, "ISH_SPI_CSB"),
PINCTRL_PIN(116, "ISH_SPI_CLK"),
PINCTRL_PIN(117, "ISH_SPI_MISO"),
PINCTRL_PIN(118, "ISH_SPI_MOSI"),
PINCTRL_PIN(119, "ISH_UART0_RXD"),
PINCTRL_PIN(120, "ISH_UART0_TXD"),
PINCTRL_PIN(121, "ISH_UART0_RTSB"),
PINCTRL_PIN(122, "ISH_UART0_CTSB"),
PINCTRL_PIN(123, "SPI1_IO_2"),
PINCTRL_PIN(124, "SPI1_IO_3"),
PINCTRL_PIN(125, "I2S_MCLK"),
PINCTRL_PIN(126, "CNV_MFUART2_RXD"),
PINCTRL_PIN(127, "CNV_MFUART2_TXD"),
PINCTRL_PIN(128, "CNV_PA_BLANKING"),
PINCTRL_PIN(129, "I2C5_SDA"),
PINCTRL_PIN(130, "I2C5_SCL"),
PINCTRL_PIN(131, "GSPI2_CLK_LOOPBK"),
PINCTRL_PIN(132, "SPI1_CLK_LOOPBK"),
PINCTRL_PIN(116, "SPI1_CSB"),
PINCTRL_PIN(117, "SPI1_CLK"),
PINCTRL_PIN(118, "SPI1_MISO_IO_1"),
PINCTRL_PIN(119, "SPI1_MOSI_IO_0"),
PINCTRL_PIN(120, "ISH_I2C0_SDA"),
PINCTRL_PIN(121, "ISH_I2C0_SCL"),
PINCTRL_PIN(122, "ISH_I2C1_SDA"),
PINCTRL_PIN(123, "ISH_I2C1_SCL"),
PINCTRL_PIN(124, "ISH_SPI_CSB"),
PINCTRL_PIN(125, "ISH_SPI_CLK"),
PINCTRL_PIN(126, "ISH_SPI_MISO"),
PINCTRL_PIN(127, "ISH_SPI_MOSI"),
PINCTRL_PIN(128, "ISH_UART0_RXD"),
PINCTRL_PIN(129, "ISH_UART0_TXD"),
PINCTRL_PIN(130, "ISH_UART0_RTSB"),
PINCTRL_PIN(131, "ISH_UART0_CTSB"),
PINCTRL_PIN(132, "SPI1_IO_2"),
PINCTRL_PIN(133, "SPI1_IO_3"),
PINCTRL_PIN(134, "I2S_MCLK"),
PINCTRL_PIN(135, "CNV_MFUART2_RXD"),
PINCTRL_PIN(136, "CNV_MFUART2_TXD"),
PINCTRL_PIN(137, "CNV_PA_BLANKING"),
PINCTRL_PIN(138, "I2C5_SDA"),
PINCTRL_PIN(139, "I2C5_SCL"),
PINCTRL_PIN(140, "GSPI2_CLK_LOOPBK"),
PINCTRL_PIN(141, "SPI1_CLK_LOOPBK"),
/* vGPIO */
PINCTRL_PIN(133, "CNV_BTEN"),
PINCTRL_PIN(134, "CNV_WCEN"),
PINCTRL_PIN(135, "CNV_BT_HOST_WAKEB"),
PINCTRL_PIN(136, "CNV_BT_IF_SELECT"),
PINCTRL_PIN(137, "vCNV_BT_UART_TXD"),
PINCTRL_PIN(138, "vCNV_BT_UART_RXD"),
PINCTRL_PIN(139, "vCNV_BT_UART_CTS_B"),
PINCTRL_PIN(140, "vCNV_BT_UART_RTS_B"),
PINCTRL_PIN(141, "vCNV_MFUART1_TXD"),
PINCTRL_PIN(142, "vCNV_MFUART1_RXD"),
PINCTRL_PIN(143, "vCNV_MFUART1_CTS_B"),
PINCTRL_PIN(144, "vCNV_MFUART1_RTS_B"),
PINCTRL_PIN(145, "vUART0_TXD"),
PINCTRL_PIN(146, "vUART0_RXD"),
PINCTRL_PIN(147, "vUART0_CTS_B"),
PINCTRL_PIN(148, "vUART0_RTS_B"),
PINCTRL_PIN(149, "vISH_UART0_TXD"),
PINCTRL_PIN(150, "vISH_UART0_RXD"),
PINCTRL_PIN(151, "vISH_UART0_CTS_B"),
PINCTRL_PIN(152, "vISH_UART0_RTS_B"),
PINCTRL_PIN(153, "vCNV_BT_I2S_BCLK"),
PINCTRL_PIN(154, "vCNV_BT_I2S_WS_SYNC"),
PINCTRL_PIN(155, "vCNV_BT_I2S_SDO"),
PINCTRL_PIN(156, "vCNV_BT_I2S_SDI"),
PINCTRL_PIN(157, "vI2S2_SCLK"),
PINCTRL_PIN(158, "vI2S2_SFRM"),
PINCTRL_PIN(159, "vI2S2_TXD"),
PINCTRL_PIN(160, "vI2S2_RXD"),
PINCTRL_PIN(161, "vSD3_CD_B"),
PINCTRL_PIN(142, "CNV_BTEN"),
PINCTRL_PIN(143, "CNV_WCEN"),
PINCTRL_PIN(144, "CNV_BT_HOST_WAKEB"),
PINCTRL_PIN(145, "CNV_BT_IF_SELECT"),
PINCTRL_PIN(146, "vCNV_BT_UART_TXD"),
PINCTRL_PIN(147, "vCNV_BT_UART_RXD"),
PINCTRL_PIN(148, "vCNV_BT_UART_CTS_B"),
PINCTRL_PIN(149, "vCNV_BT_UART_RTS_B"),
PINCTRL_PIN(150, "vCNV_MFUART1_TXD"),
PINCTRL_PIN(151, "vCNV_MFUART1_RXD"),
PINCTRL_PIN(152, "vCNV_MFUART1_CTS_B"),
PINCTRL_PIN(153, "vCNV_MFUART1_RTS_B"),
PINCTRL_PIN(154, "vUART0_TXD"),
PINCTRL_PIN(155, "vUART0_RXD"),
PINCTRL_PIN(156, "vUART0_CTS_B"),
PINCTRL_PIN(157, "vUART0_RTS_B"),
PINCTRL_PIN(158, "vISH_UART0_TXD"),
PINCTRL_PIN(159, "vISH_UART0_RXD"),
PINCTRL_PIN(160, "vISH_UART0_CTS_B"),
PINCTRL_PIN(161, "vISH_UART0_RTS_B"),
PINCTRL_PIN(162, "vCNV_BT_I2S_BCLK"),
PINCTRL_PIN(163, "vCNV_BT_I2S_WS_SYNC"),
PINCTRL_PIN(164, "vCNV_BT_I2S_SDO"),
PINCTRL_PIN(165, "vCNV_BT_I2S_SDI"),
PINCTRL_PIN(166, "vI2S2_SCLK"),
PINCTRL_PIN(167, "vI2S2_SFRM"),
PINCTRL_PIN(168, "vI2S2_TXD"),
PINCTRL_PIN(169, "vI2S2_RXD"),
PINCTRL_PIN(170, "vSD3_CD_B"),
/* GPP_C */
PINCTRL_PIN(162, "GPPC_C_0"),
PINCTRL_PIN(163, "GPPC_C_1"),
PINCTRL_PIN(164, "GPPC_C_2"),
PINCTRL_PIN(165, "GPPC_C_3"),
PINCTRL_PIN(166, "GPPC_C_4"),
PINCTRL_PIN(167, "GPPC_C_5"),
PINCTRL_PIN(168, "SUSWARNB_SUSPWRDNACK"),
PINCTRL_PIN(169, "SUSACKB"),
PINCTRL_PIN(170, "UART0_RXD"),
PINCTRL_PIN(171, "UART0_TXD"),
PINCTRL_PIN(172, "UART0_RTSB"),
PINCTRL_PIN(173, "UART0_CTSB"),
PINCTRL_PIN(174, "UART1_RXD"),
PINCTRL_PIN(175, "UART1_TXD"),
PINCTRL_PIN(176, "UART1_RTSB"),
PINCTRL_PIN(177, "UART1_CTSB"),
PINCTRL_PIN(178, "I2C0_SDA"),
PINCTRL_PIN(179, "I2C0_SCL"),
PINCTRL_PIN(180, "I2C1_SDA"),
PINCTRL_PIN(181, "I2C1_SCL"),
PINCTRL_PIN(182, "UART2_RXD"),
PINCTRL_PIN(183, "UART2_TXD"),
PINCTRL_PIN(184, "UART2_RTSB"),
PINCTRL_PIN(185, "UART2_CTSB"),
PINCTRL_PIN(171, "GPPC_C_0"),
PINCTRL_PIN(172, "GPPC_C_1"),
PINCTRL_PIN(173, "GPPC_C_2"),
PINCTRL_PIN(174, "GPPC_C_3"),
PINCTRL_PIN(175, "GPPC_C_4"),
PINCTRL_PIN(176, "GPPC_C_5"),
PINCTRL_PIN(177, "SUSWARNB_SUSPWRDNACK"),
PINCTRL_PIN(178, "SUSACKB"),
PINCTRL_PIN(179, "UART0_RXD"),
PINCTRL_PIN(180, "UART0_TXD"),
PINCTRL_PIN(181, "UART0_RTSB"),
PINCTRL_PIN(182, "UART0_CTSB"),
PINCTRL_PIN(183, "UART1_RXD"),
PINCTRL_PIN(184, "UART1_TXD"),
PINCTRL_PIN(185, "UART1_RTSB"),
PINCTRL_PIN(186, "UART1_CTSB"),
PINCTRL_PIN(187, "I2C0_SDA"),
PINCTRL_PIN(188, "I2C0_SCL"),
PINCTRL_PIN(189, "I2C1_SDA"),
PINCTRL_PIN(190, "I2C1_SCL"),
PINCTRL_PIN(191, "UART2_RXD"),
PINCTRL_PIN(192, "UART2_TXD"),
PINCTRL_PIN(193, "UART2_RTSB"),
PINCTRL_PIN(194, "UART2_CTSB"),
/* HVCMOS */
PINCTRL_PIN(186, "L_BKLTEN"),
PINCTRL_PIN(187, "L_BKLTCTL"),
PINCTRL_PIN(188, "L_VDDEN"),
PINCTRL_PIN(189, "SYS_PWROK"),
PINCTRL_PIN(190, "SYS_RESETB"),
PINCTRL_PIN(191, "MLK_RSTB"),
PINCTRL_PIN(195, "L_BKLTEN"),
PINCTRL_PIN(196, "L_BKLTCTL"),
PINCTRL_PIN(197, "L_VDDEN"),
PINCTRL_PIN(198, "SYS_PWROK"),
PINCTRL_PIN(199, "SYS_RESETB"),
PINCTRL_PIN(200, "MLK_RSTB"),
/* GPP_E */
PINCTRL_PIN(192, "ISH_GP_0"),
PINCTRL_PIN(193, "ISH_GP_1"),
PINCTRL_PIN(194, "IMGCLKOUT_1"),
PINCTRL_PIN(195, "ISH_GP_2"),
PINCTRL_PIN(196, "IMGCLKOUT_2"),
PINCTRL_PIN(197, "SATA_LEDB"),
PINCTRL_PIN(198, "IMGCLKOUT_3"),
PINCTRL_PIN(199, "ISH_GP_3"),
PINCTRL_PIN(200, "ISH_GP_4"),
PINCTRL_PIN(201, "ISH_GP_5"),
PINCTRL_PIN(202, "ISH_GP_6"),
PINCTRL_PIN(203, "ISH_GP_7"),
PINCTRL_PIN(204, "IMGCLKOUT_4"),
PINCTRL_PIN(205, "DDPA_CTRLCLK"),
PINCTRL_PIN(206, "DDPA_CTRLDATA"),
PINCTRL_PIN(207, "DDPB_CTRLCLK"),
PINCTRL_PIN(208, "DDPB_CTRLDATA"),
PINCTRL_PIN(209, "DDPC_CTRLCLK"),
PINCTRL_PIN(210, "DDPC_CTRLDATA"),
PINCTRL_PIN(211, "IMGCLKOUT_5"),
PINCTRL_PIN(212, "CNV_BRI_DT"),
PINCTRL_PIN(213, "CNV_BRI_RSP"),
PINCTRL_PIN(214, "CNV_RGI_DT"),
PINCTRL_PIN(215, "CNV_RGI_RSP"),
PINCTRL_PIN(201, "ISH_GP_0"),
PINCTRL_PIN(202, "ISH_GP_1"),
PINCTRL_PIN(203, "IMGCLKOUT_1"),
PINCTRL_PIN(204, "ISH_GP_2"),
PINCTRL_PIN(205, "IMGCLKOUT_2"),
PINCTRL_PIN(206, "SATA_LEDB"),
PINCTRL_PIN(207, "IMGCLKOUT_3"),
PINCTRL_PIN(208, "ISH_GP_3"),
PINCTRL_PIN(209, "ISH_GP_4"),
PINCTRL_PIN(210, "ISH_GP_5"),
PINCTRL_PIN(211, "ISH_GP_6"),
PINCTRL_PIN(212, "ISH_GP_7"),
PINCTRL_PIN(213, "IMGCLKOUT_4"),
PINCTRL_PIN(214, "DDPA_CTRLCLK"),
PINCTRL_PIN(215, "DDPA_CTRLDATA"),
PINCTRL_PIN(216, "DDPB_CTRLCLK"),
PINCTRL_PIN(217, "DDPB_CTRLDATA"),
PINCTRL_PIN(218, "DDPC_CTRLCLK"),
PINCTRL_PIN(219, "DDPC_CTRLDATA"),
PINCTRL_PIN(220, "IMGCLKOUT_5"),
PINCTRL_PIN(221, "CNV_BRI_DT"),
PINCTRL_PIN(222, "CNV_BRI_RSP"),
PINCTRL_PIN(223, "CNV_RGI_DT"),
PINCTRL_PIN(224, "CNV_RGI_RSP"),
/* GPP_G */
PINCTRL_PIN(216, "SD3_CMD"),
PINCTRL_PIN(217, "SD3_D0"),
PINCTRL_PIN(218, "SD3_D1"),
PINCTRL_PIN(219, "SD3_D2"),
PINCTRL_PIN(220, "SD3_D3"),
PINCTRL_PIN(221, "SD3_CDB"),
PINCTRL_PIN(222, "SD3_CLK"),
PINCTRL_PIN(223, "SD3_WP"),
PINCTRL_PIN(225, "SD3_CMD"),
PINCTRL_PIN(226, "SD3_D0"),
PINCTRL_PIN(227, "SD3_D1"),
PINCTRL_PIN(228, "SD3_D2"),
PINCTRL_PIN(229, "SD3_D3"),
PINCTRL_PIN(230, "SD3_CDB"),
PINCTRL_PIN(231, "SD3_CLK"),
PINCTRL_PIN(232, "SD3_WP"),
};
static const struct intel_padgroup jsl_community0_gpps[] = {
JSL_GPP(0, 0, 19, 320), /* GPP_F */
JSL_GPP(1, 20, 45, 32), /* GPP_B */
JSL_GPP(2, 46, 66, 64), /* GPP_A */
JSL_GPP(3, 67, 74, 96), /* GPP_S */
JSL_GPP(4, 75, 82, 128), /* GPP_R */
JSL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP), /* SPI */
JSL_GPP(2, 29, 54, 32), /* GPP_B */
JSL_GPP(3, 55, 75, 64), /* GPP_A */
JSL_GPP(4, 76, 83, 96), /* GPP_S */
JSL_GPP(5, 84, 91, 128), /* GPP_R */
};
static const struct intel_padgroup jsl_community1_gpps[] = {
JSL_GPP(0, 83, 106, 160), /* GPP_H */
JSL_GPP(1, 107, 132, 192), /* GPP_D */
JSL_GPP(2, 133, 161, 224), /* vGPIO */
JSL_GPP(3, 162, 185, 256), /* GPP_C */
JSL_GPP(0, 92, 115, 160), /* GPP_H */
JSL_GPP(1, 116, 141, 192), /* GPP_D */
JSL_GPP(2, 142, 170, 224), /* vGPIO */
JSL_GPP(3, 171, 194, 256), /* GPP_C */
};
static const struct intel_padgroup jsl_community4_gpps[] = {
JSL_GPP(0, 186, 191, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
JSL_GPP(1, 192, 215, 288), /* GPP_E */
JSL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
JSL_GPP(1, 201, 224, 288), /* GPP_E */
};
static const struct intel_padgroup jsl_community5_gpps[] = {
JSL_GPP(0, 216, 223, INTEL_GPIO_BASE_ZERO), /* GPP_G */
JSL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO), /* GPP_G */
};
static const struct intel_community jsl_communities[] = {
JSL_COMMUNITY(0, 0, 82, jsl_community0_gpps),
JSL_COMMUNITY(1, 83, 185, jsl_community1_gpps),
JSL_COMMUNITY(2, 186, 215, jsl_community4_gpps),
JSL_COMMUNITY(3, 216, 223, jsl_community5_gpps),
JSL_COMMUNITY(0, 0, 91, jsl_community0_gpps),
JSL_COMMUNITY(1, 92, 194, jsl_community1_gpps),
JSL_COMMUNITY(2, 195, 224, jsl_community4_gpps),
JSL_COMMUNITY(3, 225, 232, jsl_community5_gpps),
};
static const struct intel_pinctrl_soc_data jsl_soc_data = {
@@ -336,7 +347,6 @@ static struct platform_driver jsl_pinctrl_driver = {
.pm = &jsl_pinctrl_pm_ops,
},
};
module_platform_driver(jsl_pinctrl_driver);
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");

8
drivers/pinctrl/intel/pinctrl-merrifield.c
View File

@@ -745,6 +745,10 @@ static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin,
mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
bits |= BUFCFG_PU_EN;
/* Set default strength value in case none is given */
if (arg == 1)
arg = 20000;
switch (arg) {
case 50000:
bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
@@ -765,6 +769,10 @@ static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin,
mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
bits |= BUFCFG_PD_EN;
/* Set default strength value in case none is given */
if (arg == 1)
arg = 20000;
switch (arg) {
case 50000:
bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;

7
drivers/pinctrl/pinctrl-amd.c
View File

@@ -429,7 +429,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
@@ -437,7 +436,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
@@ -445,7 +443,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
@@ -453,8 +450,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_level_irq);
break;
@@ -462,8 +457,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_level_irq);
break;

8
fs/proc/task_mmu.c
View File

@@ -1661,11 +1661,15 @@ static ssize_t pagemap_read(struct file *file, char __user *buf,
src = *ppos;
svpfn = src / PM_ENTRY_BYTES;
start_vaddr = svpfn << PAGE_SHIFT;
end_vaddr = mm->task_size;
/* watch out for wraparound */
if (svpfn > mm->task_size >> PAGE_SHIFT)
start_vaddr = end_vaddr;
if (svpfn <= (ULONG_MAX >> PAGE_SHIFT))
start_vaddr = untagged_addr(svpfn << PAGE_SHIFT);
/* Ensure the address is inside the task */
if (start_vaddr > mm->task_size)
start_vaddr = end_vaddr;
/*

14
fs/zonefs/super.c
View File

@@ -691,21 +691,23 @@ static ssize_t zonefs_file_dio_append(struct kiocb *iocb, struct iov_iter *from)
bio->bi_opf |= REQ_FUA;
ret = bio_iov_iter_get_pages(bio, from);
if (unlikely(ret)) {
bio_io_error(bio);
return ret;
}
if (unlikely(ret))
goto out_release;
size = bio->bi_iter.bi_size;
task_io_account_write(ret);
task_io_account_write(size);
if (iocb->ki_flags & IOCB_HIPRI)
bio_set_polled(bio, iocb);
ret = submit_bio_wait(bio);
zonefs_file_write_dio_end_io(iocb, size, ret, 0);
out_release:
bio_release_pages(bio, false);
bio_put(bio);
zonefs_file_write_dio_end_io(iocb, size, ret, 0);
if (ret >= 0) {
iocb->ki_pos += size;
return size;

5
include/linux/build_bug.h
View File

@@ -77,4 +77,9 @@
#define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr)
#define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
#ifdef __GENKSYMS__
/* genksyms gets confused by _Static_assert */
#define _Static_assert(expr, ...)
#endif
#endif /* _LINUX_BUILD_BUG_H */

22
include/linux/elfcore.h
View File

@@ -104,6 +104,7 @@ static inline int elf_core_copy_task_fpregs(struct task_struct *t, struct pt_reg
#endif
}
#if defined(CONFIG_UM) || defined(CONFIG_IA64)
/*
* These functions parameterize elf_core_dump in fs/binfmt_elf.c to write out
* extra segments containing the gate DSO contents. Dumping its
@@ -118,5 +119,26 @@ elf_core_write_extra_phdrs(struct coredump_params *cprm, loff_t offset);
extern int
elf_core_write_extra_data(struct coredump_params *cprm);
extern size_t elf_core_extra_data_size(void);
#else
static inline Elf_Half elf_core_extra_phdrs(void)
{
return 0;
}
static inline int elf_core_write_extra_phdrs(struct coredump_params *cprm, loff_t offset)
{
return 1;
}
static inline int elf_core_write_extra_data(struct coredump_params *cprm)
{
return 1;
}
static inline size_t elf_core_extra_data_size(void)
{
return 0;
}
#endif
#endif /* _LINUX_ELFCORE_H */

4
include/uapi/linux/bpf.h
View File

@@ -3897,8 +3897,8 @@ union bpf_attr {
FN(seq_printf_btf), \
FN(skb_cgroup_classid), \
FN(redirect_neigh), \
FN(bpf_per_cpu_ptr), \
FN(bpf_this_cpu_ptr), \
FN(per_cpu_ptr), \
FN(this_cpu_ptr), \
FN(redirect_peer), \
/* */

2
init/initramfs.c
View File

@@ -535,7 +535,7 @@ extern unsigned long __initramfs_size;
#include <linux/initrd.h>
#include <linux/kexec.h>
void __weak free_initrd_mem(unsigned long start, unsigned long end)
void __weak __init free_initrd_mem(unsigned long start, unsigned long end)
{
#ifdef CONFIG_ARCH_KEEP_MEMBLOCK
unsigned long aligned_start = ALIGN_DOWN(start, PAGE_SIZE);

1
kernel/Makefile
View File

@@ -97,7 +97,6 @@ obj-$(CONFIG_TASK_DELAY_ACCT) += delayacct.o
obj-$(CONFIG_TASKSTATS) += taskstats.o tsacct.o
obj-$(CONFIG_TRACEPOINTS) += tracepoint.o
obj-$(CONFIG_LATENCYTOP) += latencytop.o
obj-$(CONFIG_ELFCORE) += elfcore.o
obj-$(CONFIG_FUNCTION_TRACER) += trace/
obj-$(CONFIG_TRACING) += trace/
obj-$(CONFIG_TRACE_CLOCK) += trace/

4
kernel/bpf/helpers.c
View File

@@ -717,9 +717,9 @@ bpf_base_func_proto(enum bpf_func_id func_id)
return &bpf_snprintf_btf_proto;
case BPF_FUNC_jiffies64:
return &bpf_jiffies64_proto;
case BPF_FUNC_bpf_per_cpu_ptr:
case BPF_FUNC_per_cpu_ptr:
return &bpf_per_cpu_ptr_proto;
case BPF_FUNC_bpf_this_cpu_ptr:
case BPF_FUNC_this_cpu_ptr:
return &bpf_this_cpu_ptr_proto;
default:
break;

26
kernel/elfcore.c
View File

@@ -1,26 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/elf.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/binfmts.h>
#include <linux/elfcore.h>
Elf_Half __weak elf_core_extra_phdrs(void)
{
return 0;
}
int __weak elf_core_write_extra_phdrs(struct coredump_params *cprm, loff_t offset)
{
return 1;
}
int __weak elf_core_write_extra_data(struct coredump_params *cprm)
{
return 1;
}
size_t __weak elf_core_extra_data_size(void)
{
return 0;
}

4
kernel/trace/bpf_trace.c
View File

@@ -1337,9 +1337,9 @@ bpf_tracing_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog)
return prog->aux->sleepable ? &bpf_copy_from_user_proto : NULL;
case BPF_FUNC_snprintf_btf:
return &bpf_snprintf_btf_proto;
case BPF_FUNC_bpf_per_cpu_ptr:
case BPF_FUNC_per_cpu_ptr:
return &bpf_per_cpu_ptr_proto;
case BPF_FUNC_bpf_this_cpu_ptr:
case BPF_FUNC_this_cpu_ptr:
return &bpf_this_cpu_ptr_proto;
default:
return NULL;

3
lib/Makefile
View File

@@ -107,7 +107,7 @@ obj-$(CONFIG_TEST_FREE_PAGES) += test_free_pages.o
# off the generation of FPU/SSE* instructions for kernel proper but FPU_FLAGS
# get appended last to CFLAGS and thus override those previous compiler options.
#
FPU_CFLAGS := -mhard-float -msse -msse2
FPU_CFLAGS := -msse -msse2
ifdef CONFIG_CC_IS_GCC
# Stack alignment mismatch, proceed with caution.
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -120,6 +120,7 @@ ifdef CONFIG_CC_IS_GCC
# -mpreferred-stack-boundary=3 is not between 4 and 12
#
# can be triggered. Otherwise gcc doesn't complain.
FPU_CFLAGS += -mhard-float
FPU_CFLAGS += $(call cc-option,-msse -mpreferred-stack-boundary=3,-mpreferred-stack-boundary=4)
endif

2
mm/filemap.c
View File

@@ -827,7 +827,7 @@ int replace_page_cache_page(struct page *old, struct page *new, gfp_t gfp_mask)
}
EXPORT_SYMBOL_GPL(replace_page_cache_page);
static noinline int __add_to_page_cache_locked(struct page *page,
noinline int __add_to_page_cache_locked(struct page *page,
struct address_space *mapping,
pgoff_t offset, gfp_t gfp,
void **shadowp)

1
mm/hugetlb.c
View File

@@ -1216,6 +1216,7 @@ static void destroy_compound_gigantic_page(struct page *page,
}
set_compound_order(page, 0);
page[1].compound_nr = 0;
__ClearPageHead(page);
}

39
mm/kasan/quarantine.c
View File

@@ -29,6 +29,7 @@
#include <linux/srcu.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/cpuhotplug.h>
#include "../slab.h"
#include "kasan.h"
@@ -43,6 +44,7 @@ struct qlist_head {
struct qlist_node *head;
struct qlist_node *tail;
size_t bytes;
bool offline;
};
#define QLIST_INIT { NULL, NULL, 0 }
@@ -188,6 +190,10 @@ void quarantine_put(struct kasan_free_meta *info, struct kmem_cache *cache)
local_irq_save(flags);
q = this_cpu_ptr(&cpu_quarantine);
if (q->offline) {
local_irq_restore(flags);
return;
}
qlist_put(q, &info->quarantine_link, cache->size);
if (unlikely(q->bytes > QUARANTINE_PERCPU_SIZE)) {
qlist_move_all(q, &temp);
@@ -328,3 +334,36 @@ void quarantine_remove_cache(struct kmem_cache *cache)
synchronize_srcu(&remove_cache_srcu);
}
static int kasan_cpu_online(unsigned int cpu)
{
this_cpu_ptr(&cpu_quarantine)->offline = false;
return 0;
}
static int kasan_cpu_offline(unsigned int cpu)
{
struct qlist_head *q;
q = this_cpu_ptr(&cpu_quarantine);
/* Ensure the ordering between the writing to q->offline and
* qlist_free_all. Otherwise, cpu_quarantine may be corrupted
* by interrupt.
*/
WRITE_ONCE(q->offline, true);
barrier();
qlist_free_all(q, NULL);
return 0;
}
static int __init kasan_cpu_quarantine_init(void)
{
int ret = 0;
ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "mm/kasan:online",
kasan_cpu_online, kasan_cpu_offline);
if (ret < 0)
pr_err("kasan cpu quarantine register failed [%d]\n", ret);
return ret;
}
late_initcall(kasan_cpu_quarantine_init);

4
tools/include/uapi/linux/bpf.h
View File

@@ -3897,8 +3897,8 @@ union bpf_attr {
FN(seq_printf_btf), \
FN(skb_cgroup_classid), \
FN(redirect_neigh), \
FN(bpf_per_cpu_ptr), \
FN(bpf_this_cpu_ptr), \
FN(per_cpu_ptr), \
FN(this_cpu_ptr), \
FN(redirect_peer), \
/* */