qed: Utilize FW 8.10.3.0
The New QED firmware contains several fixes, including: - Wrong classification of packets in 4-port devices. - Anti-spoof interoperability with encapsulated packets. - Tx-switching of encapsulated packets. It also slightly improves Tx performance of the device. In addition, this firmware contains the necessary logic for supporting iscsi & rdma, for which we plan on pushing protocol drivers in the imminent future. Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yuval Mintz
committed by
David S. Miller
David S. Miller
parent
b87ab6b8e5
commit
351a4dedb3
@@ -13,9 +13,19 @@
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#define X_FINAL_CLEANUP_AGG_INT 1
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/* Queue Zone sizes in bytes */
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#define TSTORM_QZONE_SIZE 8
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#define MSTORM_QZONE_SIZE 0
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#define USTORM_QZONE_SIZE 8
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#define XSTORM_QZONE_SIZE 8
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#define YSTORM_QZONE_SIZE 0
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#define PSTORM_QZONE_SIZE 0
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#define ETH_MAX_NUM_RX_QUEUES_PER_VF 16
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#define FW_MAJOR_VERSION 8
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#define FW_MINOR_VERSION 7
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#define FW_REVISION_VERSION 3
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#define FW_MINOR_VERSION 10
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#define FW_REVISION_VERSION 5
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#define FW_ENGINEERING_VERSION 0
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/***********************/
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@@ -97,45 +107,86 @@
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#define DQ_XCM_AGG_VAL_SEL_REG6 7
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/* XCM agg val selection */
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#define DQ_XCM_ETH_EDPM_NUM_BDS_CMD \
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DQ_XCM_AGG_VAL_SEL_WORD2
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#define DQ_XCM_ETH_TX_BD_CONS_CMD \
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DQ_XCM_AGG_VAL_SEL_WORD3
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#define DQ_XCM_CORE_TX_BD_CONS_CMD \
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DQ_XCM_AGG_VAL_SEL_WORD3
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#define DQ_XCM_ETH_TX_BD_PROD_CMD \
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DQ_XCM_AGG_VAL_SEL_WORD4
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#define DQ_XCM_CORE_TX_BD_PROD_CMD \
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DQ_XCM_AGG_VAL_SEL_WORD4
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#define DQ_XCM_CORE_SPQ_PROD_CMD \
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DQ_XCM_AGG_VAL_SEL_WORD4
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#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
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#define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
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#define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
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#define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
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#define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2
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#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
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#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
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#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
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/* UCM agg val selection (HW) */
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#define DQ_UCM_AGG_VAL_SEL_WORD0 0
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#define DQ_UCM_AGG_VAL_SEL_WORD1 1
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#define DQ_UCM_AGG_VAL_SEL_WORD2 2
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#define DQ_UCM_AGG_VAL_SEL_WORD3 3
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#define DQ_UCM_AGG_VAL_SEL_REG0 4
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#define DQ_UCM_AGG_VAL_SEL_REG1 5
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#define DQ_UCM_AGG_VAL_SEL_REG2 6
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#define DQ_UCM_AGG_VAL_SEL_REG3 7
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/* UCM agg val selection (FW) */
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#define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2
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#define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3
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#define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0
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#define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2
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/* TCM agg val selection (HW) */
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#define DQ_TCM_AGG_VAL_SEL_WORD0 0
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#define DQ_TCM_AGG_VAL_SEL_WORD1 1
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#define DQ_TCM_AGG_VAL_SEL_WORD2 2
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#define DQ_TCM_AGG_VAL_SEL_WORD3 3
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#define DQ_TCM_AGG_VAL_SEL_REG1 4
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#define DQ_TCM_AGG_VAL_SEL_REG2 5
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#define DQ_TCM_AGG_VAL_SEL_REG6 6
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#define DQ_TCM_AGG_VAL_SEL_REG9 7
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/* TCM agg val selection (FW) */
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#define DQ_TCM_L2B_BD_PROD_CMD \
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DQ_TCM_AGG_VAL_SEL_WORD1
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#define DQ_TCM_ROCE_RQ_PROD_CMD \
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DQ_TCM_AGG_VAL_SEL_WORD0
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/* XCM agg counter flag selection */
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#define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
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#define DQ_XCM_AGG_FLG_SHIFT_BIT15 1
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#define DQ_XCM_AGG_FLG_SHIFT_CF12 2
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#define DQ_XCM_AGG_FLG_SHIFT_CF13 3
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#define DQ_XCM_AGG_FLG_SHIFT_CF18 4
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#define DQ_XCM_AGG_FLG_SHIFT_CF19 5
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#define DQ_XCM_AGG_FLG_SHIFT_CF22 6
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#define DQ_XCM_AGG_FLG_SHIFT_CF23 7
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#define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
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#define DQ_XCM_AGG_FLG_SHIFT_BIT15 1
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#define DQ_XCM_AGG_FLG_SHIFT_CF12 2
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#define DQ_XCM_AGG_FLG_SHIFT_CF13 3
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#define DQ_XCM_AGG_FLG_SHIFT_CF18 4
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#define DQ_XCM_AGG_FLG_SHIFT_CF19 5
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#define DQ_XCM_AGG_FLG_SHIFT_CF22 6
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#define DQ_XCM_AGG_FLG_SHIFT_CF23 7
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/* XCM agg counter flag selection */
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#define DQ_XCM_ETH_DQ_CF_CMD (1 << \
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DQ_XCM_AGG_FLG_SHIFT_CF18)
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#define DQ_XCM_CORE_DQ_CF_CMD (1 << \
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DQ_XCM_AGG_FLG_SHIFT_CF18)
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#define DQ_XCM_ETH_TERMINATE_CMD (1 << \
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DQ_XCM_AGG_FLG_SHIFT_CF19)
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#define DQ_XCM_CORE_TERMINATE_CMD (1 << \
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DQ_XCM_AGG_FLG_SHIFT_CF19)
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#define DQ_XCM_ETH_SLOW_PATH_CMD (1 << \
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DQ_XCM_AGG_FLG_SHIFT_CF22)
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#define DQ_XCM_CORE_SLOW_PATH_CMD (1 << \
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DQ_XCM_AGG_FLG_SHIFT_CF22)
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#define DQ_XCM_ETH_TPH_EN_CMD (1 << \
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DQ_XCM_AGG_FLG_SHIFT_CF23)
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#define DQ_XCM_CORE_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18)
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#define DQ_XCM_CORE_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
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#define DQ_XCM_CORE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
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#define DQ_XCM_ETH_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18)
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#define DQ_XCM_ETH_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
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#define DQ_XCM_ETH_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
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#define DQ_XCM_ETH_TPH_EN_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23)
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/* UCM agg counter flag selection (HW) */
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#define DQ_UCM_AGG_FLG_SHIFT_CF0 0
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#define DQ_UCM_AGG_FLG_SHIFT_CF1 1
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#define DQ_UCM_AGG_FLG_SHIFT_CF3 2
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#define DQ_UCM_AGG_FLG_SHIFT_CF4 3
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#define DQ_UCM_AGG_FLG_SHIFT_CF5 4
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#define DQ_UCM_AGG_FLG_SHIFT_CF6 5
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#define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6
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#define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7
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/* UCM agg counter flag selection (FW) */
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#define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
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#define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
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#define DQ_REGION_SHIFT (12)
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/* DPM */
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#define DQ_DPM_WQE_BUFF_SIZE (320)
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/* Conn type ranges */
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#define DQ_CONN_TYPE_RANGE_SHIFT (4)
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/*****************/
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/* QM CONSTANTS */
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@@ -282,8 +333,6 @@
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(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
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PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
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#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
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#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
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#define PXP_VF_BAR0_START_IGU 0
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#define PXP_VF_BAR0_IGU_LENGTH 0x3000
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@@ -342,6 +391,9 @@
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#define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
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#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
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#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
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/* ILT Records */
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#define PXP_NUM_ILT_RECORDS_BB 7600
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#define PXP_NUM_ILT_RECORDS_K2 11000
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@@ -379,6 +431,38 @@ struct async_data {
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u8 fw_debug_param;
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};
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struct coalescing_timeset {
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u8 value;
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#define COALESCING_TIMESET_TIMESET_MASK 0x7F
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#define COALESCING_TIMESET_TIMESET_SHIFT 0
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#define COALESCING_TIMESET_VALID_MASK 0x1
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#define COALESCING_TIMESET_VALID_SHIFT 7
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};
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struct common_prs_pf_msg_info {
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__le32 value;
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#define COMMON_PRS_PF_MSG_INFO_NPAR_DEFAULT_PF_MASK 0x1
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#define COMMON_PRS_PF_MSG_INFO_NPAR_DEFAULT_PF_SHIFT 0
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#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_1_MASK 0x1
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#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_1_SHIFT 1
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#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_2_MASK 0x1
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#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_2_SHIFT 2
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#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_3_MASK 0x1
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#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_3_SHIFT 3
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#define COMMON_PRS_PF_MSG_INFO_RESERVED_MASK 0xFFFFFFF
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#define COMMON_PRS_PF_MSG_INFO_RESERVED_SHIFT 4
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};
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struct common_queue_zone {
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__le16 ring_drv_data_consumer;
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__le16 reserved;
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};
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struct eth_rx_prod_data {
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__le16 bd_prod;
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__le16 cqe_prod;
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};
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struct regpair {
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__le32 lo;
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__le32 hi;
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@@ -388,11 +472,23 @@ struct vf_pf_channel_eqe_data {
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struct regpair msg_addr;
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};
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struct malicious_vf_eqe_data {
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u8 vf_id;
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u8 err_id;
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__le16 reserved[3];
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};
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struct initial_cleanup_eqe_data {
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u8 vf_id;
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u8 reserved[7];
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};
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/* Event Data Union */
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union event_ring_data {
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u8 bytes[8];
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struct vf_pf_channel_eqe_data vf_pf_channel;
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struct async_data async_info;
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u8 bytes[8];
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struct vf_pf_channel_eqe_data vf_pf_channel;
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struct malicious_vf_eqe_data malicious_vf;
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struct initial_cleanup_eqe_data vf_init_cleanup;
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};
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/* Event Ring Entry */
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@@ -433,6 +529,16 @@ enum protocol_type {
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MAX_PROTOCOL_TYPE
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};
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struct ustorm_eth_queue_zone {
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struct coalescing_timeset int_coalescing_timeset;
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u8 reserved[3];
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};
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struct ustorm_queue_zone {
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struct ustorm_eth_queue_zone eth;
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struct common_queue_zone common;
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};
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/* status block structure */
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struct cau_pi_entry {
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u32 prod;
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@@ -683,19 +789,4 @@ struct status_block {
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#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
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};
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struct tunnel_parsing_flags {
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u8 flags;
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#define TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
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#define TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
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#define TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
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#define TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
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#define TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
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#define TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
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#define TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
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#define TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
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#define TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
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#define TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
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#define TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
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#define TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
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};
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#endif /* __COMMON_HSI__ */
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