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[MIPS] Support for the RM9000-based Basler eXcite smart camera platform.

Sfoglia il codice sorgente 
Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2006-06-18 16:39:46 +01:00
parent 355c471f2f
commit 35189fad3c
27 ha cambiato i file con 3528 aggiunte e 9 eliminazioni
Scarica il file Patch Scarica il file Diff Expand all files Collapse all files

1
arch/mips/pci/Makefile
Vedi File

@@ -23,6 +23,7 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
#
# These are still pretty much in the old state, watch, go blind.
#
obj-$(CONFIG_BASLER_EXCITE) = ops-titan.o pci-excite.o fixup-excite.o
obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
obj-$(CONFIG_LASAT) += pci-lasat.o
obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o

36
arch/mips/pci/fixup-excite.c Normal file
Vedi File

@@ -0,0 +1,36 @@
/*
* Copyright (C) 2004 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <excite.h>
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
if (pin == 0)
return -1;
return USB_IRQ; /* USB controller is the only PCI device */
}
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}

25
arch/mips/pci/ops-titan.c
Vedi File

@@ -26,8 +26,19 @@
#include <linux/pci.h>
#include <linux/kernel.h>
#include <asm/titan_dep.h>
#include <asm/pci.h>
#include <asm/io.h>
#include <asm/rm9k-ocd.h>
/*
* PCI specific defines
*/
#define TITAN_PCI_0_CONFIG_ADDRESS 0x780
#define TITAN_PCI_0_CONFIG_DATA 0x784
/*
* Titan PCI Config Read Byte
*/
static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
int size, u32 * val)
{
@@ -43,8 +54,8 @@ static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
/* start the configuration cycle */
TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address);
tmp = TITAN_READ(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
tmp = ocd_readl(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
switch (size) {
case 1:
@@ -71,20 +82,20 @@ static int titan_write_config(struct pci_bus *bus, unsigned int devfn, int reg,
(reg & 0xfc) | 0x80000000;
/* start the configuration cycle */
TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address);
ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
/* write the data */
switch (size) {
case 1:
TITAN_WRITE_8(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3), val);
ocd_writeb(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3));
break;
case 2:
TITAN_WRITE_16(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2), val);
ocd_writew(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2));
break;
case 4:
TITAN_WRITE(TITAN_PCI_0_CONFIG_DATA, val);
ocd_writel(val, TITAN_PCI_0_CONFIG_DATA);
break;
}

149
arch/mips/pci/pci-excite.c Normal file
Vedi File

@@ -0,0 +1,149 @@
/*
* Copyright (C) 2004 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
* Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/bitops.h>
#include <asm/rm9k-ocd.h>
#include <excite.h>
extern struct pci_ops titan_pci_ops;
static struct resource
mem_resource = {
.name = "PCI memory",
.start = EXCITE_PHYS_PCI_MEM,
.end = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
.flags = IORESOURCE_MEM
},
io_resource = {
.name = "PCI I/O",
.start = EXCITE_PHYS_PCI_IO,
.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
.flags = IORESOURCE_IO
};
static struct pci_controller bx_controller = {
.pci_ops = &titan_pci_ops,
.mem_resource = &mem_resource,
.mem_offset = 0x00000000UL,
.io_resource = &io_resource,
.io_offset = 0x00000000UL
};
static char
iopage_failed[] __initdata = "Cannot allocate PCI I/O page",
modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
#define RM9000x2_OCD_HTSC 0x0604
#define RM9000x2_OCD_HTBHL 0x060c
#define RM9000x2_OCD_PCIHRST 0x078c
#define RM9K_OCD_MODEBIT1 0x00d4 /* (MODEBIT1) Mode Bit 1 */
#define RM9K_OCD_CPHDCR 0x00f4 /* CPU-PCI/HT Data Control. */
#define PCISC_FB2B 0x00000200
#define PCISC_MWICG 0x00000010
#define PCISC_EMC 0x00000004
#define PCISC_ERMA 0x00000002
static int __init basler_excite_pci_setup(void)
{
const unsigned int fullbars = memsize / (256 << 20);
unsigned int i;
/* Check modebits to see if PCI is really enabled. */
if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
panic(modebits_no_pci);
if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
"Memory-mapped PCI I/O page"))
panic(iopage_failed);
/* Enable PCI 0 as master for config cycles */
ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
/* Set up latency timer */
ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
/* Setup host IO and Memory space */
ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
/* Set up PCI BARs to map all installed memory */
for (i = 0; i < 6; i++) {
const unsigned int bar = 0x610 + i * 4;
if (i < fullbars) {
ocd_writel(0x10000000 * i, bar);
ocd_writel(0x01000000 * i, bar + 0x140);
ocd_writel(0x0ffff029, bar + 0x100);
continue;
}
if (i == fullbars) {
int o;
u32 mask;
const unsigned long rem = memsize - i * 0x10000000;
if (!rem) {
ocd_writel(0x00000000, bar + 0x100);
continue;
}
o = ffs(rem) - 1;
if (rem & ~(0x1 << o))
o++;
mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
ocd_writel(0x10000000 * i, bar);
ocd_writel(0x01000000 * i, bar + 0x140);
ocd_writel(0x00000029 | mask, bar + 0x100);
continue;
}
ocd_writel(0x00000000, bar + 0x100);
}
/* Finally, enable the PCI interupt */
#if USB_IRQ > 7
set_c0_intcontrol(1 << USB_IRQ);
#else
set_c0_status(1 << (USB_IRQ + 8));
#endif
ioport_resource.start = EXCITE_PHYS_PCI_IO;
ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
register_pci_controller(&bx_controller);
return 0;
}
arch_initcall(basler_excite_pci_setup);