net/mlx5: DR, Don't use SW steering when RoCE is not supported

[ Upstream commit 4aaf96ac8b45d8e2e019b6b53cce65a73c4ace2c ]

SW steering uses RC QP to write/read to/from ICM, hence it's not
supported when RoCE is not supported as well.

Fixes: 70605ea545 ("net/mlx5: DR, Expose APIs for direct rule managing")
Signed-off-by: Maor Gottlieb <maorg@nvidia.com>
Reviewed-by: Alex Vesker <valex@nvidia.com>
Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Maor Gottlieb
2021-06-06 11:23:41 +03:00
committed by Greg Kroah-Hartman
parent 3623bfcab3
commit 34ff3770bf

View File

@@ -124,10 +124,11 @@ int mlx5dr_action_destroy(struct mlx5dr_action *action);
static inline bool static inline bool
mlx5dr_is_supported(struct mlx5_core_dev *dev) mlx5dr_is_supported(struct mlx5_core_dev *dev)
{ {
return MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner) || return MLX5_CAP_GEN(dev, roce) &&
(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner) ||
(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner_v2) && (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner_v2) &&
(MLX5_CAP_GEN(dev, steering_format_version) <= (MLX5_CAP_GEN(dev, steering_format_version) <=
MLX5_STEERING_FORMAT_CONNECTX_6DX)); MLX5_STEERING_FORMAT_CONNECTX_6DX)));
} }
#endif /* _MLX5DR_H_ */ #endif /* _MLX5DR_H_ */