ath5k: Cleanups v1
No functional changes, just a few comments/documentation/cleanup Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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Nick Kossifidis
committed by
John W. Linville
John W. Linville
parent
fea9480786
commit
34ce644aa8
@@ -2149,69 +2149,110 @@ ath5k_intr(int irq, void *dev_id)
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enum ath5k_int status;
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unsigned int counter = 1000;
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/*
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* If hw is not ready (or detached) and we get an
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* interrupt, or if we have no interrupts pending
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* (that means it's not for us) skip it.
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*
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* NOTE: Group 0/1 PCI interface registers are not
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* supported on WiSOCs, so we can't check for pending
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* interrupts (ISR belongs to another register group
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* so we are ok).
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*/
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if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
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((ath5k_get_bus_type(ah) != ATH_AHB) &&
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!ath5k_hw_is_intr_pending(ah))))
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((ath5k_get_bus_type(ah) != ATH_AHB) &&
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!ath5k_hw_is_intr_pending(ah))))
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return IRQ_NONE;
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/** Main loop **/
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do {
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ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
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ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
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ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
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status, ah->imask);
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/*
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* Fatal hw error -> Log and reset
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*
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* Fatal errors are unrecoverable so we have to
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* reset the card. These errors include bus and
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* dma errors.
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*/
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if (unlikely(status & AR5K_INT_FATAL)) {
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/*
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* Fatal errors are unrecoverable.
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* Typically these are caused by DMA errors.
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*/
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ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
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"fatal int, resetting\n");
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ieee80211_queue_work(ah->hw, &ah->reset_work);
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/*
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* RX Overrun -> Count and reset if needed
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*
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* Receive buffers are full. Either the bus is busy or
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* the CPU is not fast enough to process all received
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* frames.
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*/
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} else if (unlikely(status & AR5K_INT_RXORN)) {
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/*
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* Receive buffers are full. Either the bus is busy or
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* the CPU is not fast enough to process all received
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* frames.
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* Older chipsets need a reset to come out of this
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* condition, but we treat it as RX for newer chips.
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* We don't know exactly which versions need a reset -
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* We don't know exactly which versions need a reset
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* this guess is copied from the HAL.
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*/
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ah->stats.rxorn_intr++;
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if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
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ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
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"rx overrun, resetting\n");
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ieee80211_queue_work(ah->hw, &ah->reset_work);
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} else
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ath5k_schedule_rx(ah);
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} else {
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/* Software Beacon Alert -> Schedule beacon tasklet */
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if (status & AR5K_INT_SWBA)
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tasklet_hi_schedule(&ah->beacontq);
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if (status & AR5K_INT_RXEOL) {
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/*
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* NB: the hardware should re-read the link when
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* RXE bit is written, but it doesn't work at
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* least on older hardware revs.
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*/
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/*
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* No more RX descriptors -> Just count
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*
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* NB: the hardware should re-read the link when
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* RXE bit is written, but it doesn't work at
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* least on older hardware revs.
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*/
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if (status & AR5K_INT_RXEOL)
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ah->stats.rxeol_intr++;
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}
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if (status & AR5K_INT_TXURN) {
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/* bump tx trigger level */
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/* TX Underrun -> Bump tx trigger level */
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if (status & AR5K_INT_TXURN)
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ath5k_hw_update_tx_triglevel(ah, true);
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}
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/* RX -> Schedule rx tasklet */
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if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
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ath5k_schedule_rx(ah);
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if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
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| AR5K_INT_TXERR | AR5K_INT_TXEOL))
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/* TX -> Schedule tx tasklet */
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if (status & (AR5K_INT_TXOK
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| AR5K_INT_TXDESC
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| AR5K_INT_TXERR
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| AR5K_INT_TXEOL))
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ath5k_schedule_tx(ah);
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if (status & AR5K_INT_BMISS) {
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/* TODO */
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}
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/* Missed beacon -> TODO
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if (status & AR5K_INT_BMISS)
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*/
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/* MIB event -> Update counters and notify ANI */
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if (status & AR5K_INT_MIB) {
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ah->stats.mib_intr++;
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ath5k_hw_update_mib_counters(ah);
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ath5k_ani_mib_intr(ah);
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}
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/* GPIO -> Notify RFKill layer */
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if (status & AR5K_INT_GPIO)
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tasklet_schedule(&ah->rf_kill.toggleq);
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@@ -2222,12 +2263,19 @@ ath5k_intr(int irq, void *dev_id)
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} while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
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/*
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* Until we handle rx/tx interrupts mask them on IMR
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*
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* NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets
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* and unset after we 've handled the interrupts.
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*/
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if (ah->rx_pending || ah->tx_pending)
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ath5k_set_current_imask(ah);
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if (unlikely(!counter))
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ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
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/* Fire up calibration poll */
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ath5k_intr_calibration_poll(ah);
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return IRQ_HANDLED;
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@@ -2544,9 +2592,15 @@ int ath5k_start(struct ieee80211_hw *hw)
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* and then setup of the interrupt mask.
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*/
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ah->curchan = ah->hw->conf.channel;
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ah->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
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AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
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AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
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ah->imask = AR5K_INT_RXOK
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| AR5K_INT_RXERR
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| AR5K_INT_RXEOL
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| AR5K_INT_RXORN
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| AR5K_INT_TXDESC
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| AR5K_INT_TXEOL
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| AR5K_INT_FATAL
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| AR5K_INT_GLOBAL
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| AR5K_INT_MIB;
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ret = ath5k_reset(ah, NULL, false);
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if (ret)
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