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drm/i915/debugfs: move uC printers and update debugfs file names

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Move the printers to the respective files for clarity. The
guc_load_status debugfs has been squashed in the guc_info one, has
having separate ones wasn't very useful. The HuC debugfs has been
renamed huc_info to match.

v2: keep printing HUC_STATUS2 (Tony), avoid const->non-const
    container_of (Jani)

Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200326181121.16869-5-daniele.ceraolospurio@intel.com
This commit is contained in:
Daniele Ceraolo Spurio
2020-03-26 11:11:19 -07:00
committed by Chris Wilson
parent 801a0caa62
commit 34904bd64a
7 changed files with 189 additions and 115 deletions
Download Patch File Download Diff File Expand all files Collapse all files

131
drivers/gpu/drm/i915/i915_debugfs.c
View File

@@ -1251,105 +1251,32 @@ static int i915_llc(struct seq_file *m, void *data)
return 0;
}
static int i915_huc_load_status_info(struct seq_file *m, void *data)
static int i915_huc_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
intel_wakeref_t wakeref;
struct drm_printer p;
struct intel_huc *huc = &dev_priv->gt.uc.huc;
struct drm_printer p = drm_seq_file_printer(m);
if (!HAS_GT_UC(dev_priv))
if (!intel_huc_is_supported(huc))
return -ENODEV;
p = drm_seq_file_printer(m);
intel_uc_fw_dump(&dev_priv->gt.uc.huc.fw, &p);
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
intel_huc_load_status(huc, &p);
return 0;
}
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
intel_wakeref_t wakeref;
struct drm_printer p;
if (!HAS_GT_UC(dev_priv))
return -ENODEV;
p = drm_seq_file_printer(m);
intel_uc_fw_dump(&dev_priv->gt.uc.guc.fw, &p);
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
u32 tmp = I915_READ(GUC_STATUS);
u32 i;
seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
seq_printf(m, "\tBootrom status = 0x%x\n",
(tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
seq_printf(m, "\tuKernel status = 0x%x\n",
(tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
seq_printf(m, "\tMIA Core status = 0x%x\n",
(tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
seq_puts(m, "\nScratch registers:\n");
for (i = 0; i < 16; i++) {
seq_printf(m, "\t%2d: \t0x%x\n",
i, I915_READ(SOFT_SCRATCH(i)));
}
}
return 0;
}
static const char *
stringify_guc_log_type(enum guc_log_buffer_type type)
{
switch (type) {
case GUC_ISR_LOG_BUFFER:
return "ISR";
case GUC_DPC_LOG_BUFFER:
return "DPC";
case GUC_CRASH_DUMP_LOG_BUFFER:
return "CRASH";
default:
MISSING_CASE(type);
}
return "";
}
static void i915_guc_log_info(struct seq_file *m, struct intel_guc_log *log)
{
enum guc_log_buffer_type type;
if (!intel_guc_log_relay_created(log)) {
seq_puts(m, "GuC log relay not created\n");
return;
}
seq_puts(m, "GuC logging stats:\n");
seq_printf(m, "\tRelay full count: %u\n",
log->relay.full_count);
for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
seq_printf(m, "\t%s:\tflush count %10u, overflow count %10u\n",
stringify_guc_log_type(type),
log->stats[type].flush,
log->stats[type].sampled_overflow);
}
}
static int i915_guc_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_uc *uc = &dev_priv->gt.uc;
struct intel_guc *guc = &dev_priv->gt.uc.guc;
struct drm_printer p = drm_seq_file_printer(m);
if (!intel_uc_uses_guc(uc))
if (!intel_guc_is_supported(guc))
return -ENODEV;
i915_guc_log_info(m, &uc->guc.log);
intel_guc_load_status(guc, &p);
drm_puts(&p, "\n");
intel_guc_log_info(&guc->log, &p);
/* Add more as required ... */
@@ -1360,39 +1287,14 @@ static int i915_guc_log_dump(struct seq_file *m, void *data)
{
struct drm_info_node *node = m->private;
struct drm_i915_private *dev_priv = node_to_i915(node);
struct intel_guc *guc = &dev_priv->gt.uc.guc;
bool dump_load_err = !!node->info_ent->data;
struct drm_i915_gem_object *obj = NULL;
u32 *log;
int i = 0;
struct drm_printer p = drm_seq_file_printer(m);
if (!HAS_GT_UC(dev_priv))
if (!intel_guc_is_supported(guc))
return -ENODEV;
if (dump_load_err)
obj = dev_priv->gt.uc.load_err_log;
else if (dev_priv->gt.uc.guc.log.vma)
obj = dev_priv->gt.uc.guc.log.vma->obj;
if (!obj)
return 0;
log = i915_gem_object_pin_map(obj, I915_MAP_WC);
if (IS_ERR(log)) {
DRM_DEBUG("Failed to pin object\n");
seq_puts(m, "(log data unaccessible)\n");
return PTR_ERR(log);
}
for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
*(log + i), *(log + i + 1),
*(log + i + 2), *(log + i + 3));
seq_putc(m, '\n');
i915_gem_object_unpin_map(obj);
return 0;
return intel_guc_log_dump(&guc->log, &p, dump_load_err);
}
static int i915_guc_log_level_get(void *data, u64 *val)
@@ -2088,10 +1990,9 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
{"i915_gem_interrupt", i915_interrupt_info, 0},
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
{"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
{"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_huc_info", i915_huc_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_ring_freq_table", i915_ring_freq_table, 0},
{"i915_context_status", i915_context_status, 0},