Merge tag 'iwlwifi-next-for-kalle-2019-02-04' of git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-next
Third batch of iwlwifi patches intended for v5.1 * Work on the new debugging infrastructure continues; * HE radiotap; * Support for new FW version 44; * A couple of new FW API changes; * A bunch of fixes for static analyzer reported issues; * General bugfixes; * Other cleanups and small fixes;
This commit is contained in:
@@ -59,8 +59,7 @@
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void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_self_init_dram *dram = &trans_pcie->init_dram;
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struct iwl_self_init_dram *dram = &trans->init_dram;
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int i;
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if (!dram->paging) {
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@@ -83,8 +82,7 @@ int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
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const struct fw_img *fw,
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struct iwl_context_info_dram *ctxt_dram)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_self_init_dram *dram = &trans_pcie->init_dram;
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struct iwl_self_init_dram *dram = &trans->init_dram;
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int i, ret, lmac_cnt, umac_cnt, paging_cnt;
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if (WARN(dram->paging,
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@@ -453,20 +453,6 @@ enum iwl_image_response_code {
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IWL_IMAGE_RESP_FAIL = 2,
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};
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/**
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* struct iwl_self_init_dram - dram data used by self init process
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* @fw: lmac and umac dram data
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* @fw_cnt: total number of items in array
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* @paging: paging dram data
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* @paging_cnt: total number of items in array
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*/
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struct iwl_self_init_dram {
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struct iwl_dram_data *fw;
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int fw_cnt;
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struct iwl_dram_data *paging;
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int paging_cnt;
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};
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/**
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* struct cont_rec: continuous recording data structure
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* @prev_wr_ptr: the last address that was read in monitor_data
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@@ -554,7 +540,6 @@ struct iwl_trans_pcie {
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dma_addr_t prph_info_dma_addr;
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dma_addr_t prph_scratch_dma_addr;
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dma_addr_t iml_dma_addr;
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struct iwl_self_init_dram init_dram;
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struct iwl_trans *trans;
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struct net_device napi_dev;
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@@ -813,8 +798,7 @@ static inline int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
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static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_self_init_dram *dram = &trans_pcie->init_dram;
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struct iwl_self_init_dram *dram = &trans->init_dram;
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int i;
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if (!dram->fw) {
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@@ -1052,6 +1036,7 @@ static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans)
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void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state);
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void iwl_trans_pcie_dump_regs(struct iwl_trans *trans);
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void iwl_trans_sync_nmi(struct iwl_trans *trans);
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#ifdef CONFIG_IWLWIFI_DEBUGFS
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int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans);
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@@ -92,26 +92,9 @@ int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
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iwl_pcie_apm_config(trans);
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/*
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* Set "initialization complete" bit to move adapter from
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* D0U* --> D0A* (powered-up active) state.
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*/
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iwl_set_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_init_done));
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/*
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* Wait for clock stabilization; once stabilized, access to
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* device-internal resources is supported, e.g. iwl_write_prph()
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* and accesses to uCode SRAM.
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*/
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_mac_clock_ready),
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BIT(trans->cfg->csr->flag_mac_clock_ready),
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25000);
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if (ret < 0) {
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IWL_DEBUG_INFO(trans, "Failed to init the card\n");
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ret = iwl_finish_nic_init(trans);
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if (ret)
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return ret;
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}
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set_bit(STATUS_DEVICE_ENABLED, &trans->status);
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@@ -364,26 +364,9 @@ static int iwl_pcie_apm_init(struct iwl_trans *trans)
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if (trans->cfg->base_params->pll_cfg)
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iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
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/*
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* Set "initialization complete" bit to move adapter from
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* D0U* --> D0A* (powered-up active) state.
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*/
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iwl_set_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_init_done));
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/*
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* Wait for clock stabilization; once stabilized, access to
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* device-internal resources is supported, e.g. iwl_write_prph()
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* and accesses to uCode SRAM.
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*/
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_mac_clock_ready),
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BIT(trans->cfg->csr->flag_mac_clock_ready),
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25000);
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if (ret < 0) {
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IWL_ERR(trans, "Failed to init the card\n");
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ret = iwl_finish_nic_init(trans);
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if (ret)
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return ret;
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}
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if (trans->cfg->host_interrupt_operation_mode) {
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/*
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@@ -453,23 +436,8 @@ static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
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iwl_trans_pcie_sw_reset(trans);
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/*
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* Set "initialization complete" bit to move adapter from
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* D0U* --> D0A* (powered-up active) state.
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*/
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iwl_set_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_init_done));
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/*
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* Wait for clock stabilization; once stabilized, access to
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* device-internal resources is possible.
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*/
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_mac_clock_ready),
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BIT(trans->cfg->csr->flag_mac_clock_ready),
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25000);
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if (WARN_ON(ret < 0)) {
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IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
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ret = iwl_finish_nic_init(trans);
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if (WARN_ON(ret)) {
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/* Release XTAL ON request */
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__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
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@@ -1558,20 +1526,10 @@ static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
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iwl_set_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_mac_access_req));
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iwl_set_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_init_done));
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if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
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udelay(2);
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_mac_clock_ready),
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BIT(trans->cfg->csr->flag_mac_clock_ready),
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25000);
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if (ret < 0) {
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IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
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ret = iwl_finish_nic_init(trans);
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if (ret)
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return ret;
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}
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/*
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* Reconfigure IVAR table in case of MSIX or reset ict table in
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@@ -3220,10 +3178,10 @@ static struct iwl_trans_dump_data
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/* Paged memory for gen2 HW */
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if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
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for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++)
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for (i = 0; i < trans->init_dram.paging_cnt; i++)
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len += sizeof(*data) +
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sizeof(struct iwl_fw_error_dump_paging) +
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trans_pcie->init_dram.paging[i].size;
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trans->init_dram.paging[i].size;
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dump_data = vzalloc(len);
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if (!dump_data)
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@@ -3275,20 +3233,16 @@ static struct iwl_trans_dump_data
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/* Paged memory for gen2 HW */
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if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
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for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) {
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for (i = 0; i < trans->init_dram.paging_cnt; i++) {
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struct iwl_fw_error_dump_paging *paging;
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dma_addr_t addr =
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trans_pcie->init_dram.paging[i].physical;
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u32 page_len = trans_pcie->init_dram.paging[i].size;
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u32 page_len = trans->init_dram.paging[i].size;
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data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
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data->len = cpu_to_le32(sizeof(*paging) + page_len);
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paging = (void *)data->data;
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paging->index = cpu_to_le32(i);
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dma_sync_single_for_cpu(trans->dev, addr, page_len,
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DMA_BIDIRECTIONAL);
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memcpy(paging->data,
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trans_pcie->init_dram.paging[i].block, page_len);
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trans->init_dram.paging[i].block, page_len);
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data = iwl_fw_error_next_data(data);
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len += sizeof(*data) + sizeof(*paging) + page_len;
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@@ -3525,18 +3479,9 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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* in-order to recognize C step driver should read chip version
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* id located at the AUX bus MISC address space.
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*/
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iwl_set_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_init_done));
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udelay(2);
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_mac_clock_ready),
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BIT(trans->cfg->csr->flag_mac_clock_ready),
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25000);
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if (ret < 0) {
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IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
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ret = iwl_finish_nic_init(trans);
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if (ret)
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goto out_no_pci;
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}
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if (iwl_trans_grab_nic_access(trans, &flags)) {
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u32 hw_step;
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@@ -3654,3 +3599,28 @@ out_no_pci:
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iwl_trans_free(trans);
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return ERR_PTR(ret);
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}
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void iwl_trans_sync_nmi(struct iwl_trans *trans)
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{
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unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
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iwl_disable_interrupts(trans);
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iwl_force_nmi(trans);
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while (time_after(timeout, jiffies)) {
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u32 inta_hw = iwl_read32(trans,
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CSR_MSIX_HW_INT_CAUSES_AD);
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/* Error detected by uCode */
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if (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR) {
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/* Clear causes register */
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iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
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inta_hw &
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MSIX_HW_INT_CAUSES_REG_SW_ERR);
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break;
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}
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mdelay(1);
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}
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iwl_enable_interrupts(trans);
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iwl_trans_fw_error(trans);
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}
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@@ -6,7 +6,7 @@
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 Intel Corporation
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* Copyright(c) 2018 - 2019 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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@@ -20,7 +20,7 @@
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* BSD LICENSE
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 Intel Corporation
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* Copyright(c) 2018 - 2019 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -965,9 +965,7 @@ static int iwl_pcie_gen2_send_hcmd_sync(struct iwl_trans *trans,
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cmd_str);
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ret = -ETIMEDOUT;
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iwl_force_nmi(trans);
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iwl_trans_fw_error(trans);
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iwl_trans_sync_nmi(trans);
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goto cancel;
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}
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@@ -8,7 +8,7 @@
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* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
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* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 Intel Corporation
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* Copyright(c) 2018 - 2019 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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@@ -31,7 +31,7 @@
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* Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
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* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 Intel Corporation
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* Copyright(c) 2018 - 2019 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -1942,9 +1942,7 @@ static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
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iwl_get_cmd_string(trans, cmd->id));
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ret = -ETIMEDOUT;
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iwl_force_nmi(trans);
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iwl_trans_fw_error(trans);
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iwl_trans_sync_nmi(trans);
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goto cancel;
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}
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