Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into clk-next
Pull Amlogic clock driver updates from Neil Armstrong: * meson8b: add the reset controller to the clkc * meson: expose all clk ids * gxbb-aoclk: Add CEC 32k clock * gxbb: add mmc input 0 clocks * meson: fix protection against undefined clks * gxbb: fix audio divider flags * tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson: clk: meson: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb-aoclk: Switch to regmap for register access dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings clk: meson: gxbb: Add sd_emmc clk0 clocks clk: meson: gxbb: fix clk_mclk_i958 divider flags clk: meson: gxbb: fix meson cts_amclk divider flags clk: meson: meson8b: register the built-in reset controller dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb: Add sd_emmc clk0 clkids clk: meson-gxbb: expose almost every clock in the bindings clk: meson8b: expose every clock in the bindings clk: meson: gxbb: fix protection against undefined clks clk: meson: meson8b: fix protection against undefined clks dt-bindings: clock: meson8b: describe the embedded reset controller
此提交包含在：
Stephen Boyd
@@ -850,13 +850,14 @@ static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
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.shift = 0,
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.width = 8,
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},
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "cts_amclk_div",
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.ops = &meson_clk_audio_divider_ops,
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.parent_names = (const char *[]){ "cts_amclk_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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@@ -880,7 +881,7 @@ static struct clk_mux gxbb_cts_mclk_i958_sel = {
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/* Default parent unknown (register reset value: 0) */
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.table = (u32[]){ 1, 2, 3 },
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.hw.init = &(struct clk_init_data) {
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.name = "cts_mclk_i958_sel",
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.ops = &clk_mux_ops,
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.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
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@@ -894,12 +895,13 @@ static struct clk_divider gxbb_cts_mclk_i958_div = {
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.shift = 16,
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.width = 8,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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.hw.init = &(struct clk_init_data) {
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.name = "cts_mclk_i958_div",
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.ops = &clk_divider_ops,
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.parent_names = (const char *[]){ "cts_mclk_i958_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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@@ -979,6 +981,156 @@ static struct clk_mux gxbb_32k_clk_sel = {
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},
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};
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static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
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"xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
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/*
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* Following these parent clocks, we should also have had mpll2, mpll3
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* and gp0_pll but these clocks are too precious to be used here. All
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* the necessary rates for MMC and NAND operation can be acheived using
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* xtal or fclk_div clocks
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*/
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};
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/* SDIO clock */
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static struct clk_mux gxbb_sd_emmc_a_clk0_sel = {
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.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
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.mask = 0x7,
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.shift = 9,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data) {
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.name = "sd_emmc_a_clk0_sel",
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.ops = &clk_mux_ops,
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.parent_names = gxbb_sd_emmc_clk0_parent_names,
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.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_divider gxbb_sd_emmc_a_clk0_div = {
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.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.lock = &clk_lock,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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.hw.init = &(struct clk_init_data) {
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.name = "sd_emmc_a_clk0_div",
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.ops = &clk_divider_ops,
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.parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_gate gxbb_sd_emmc_a_clk0 = {
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.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
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.bit_idx = 7,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "sd_emmc_a_clk0",
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
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.num_parents = 1,
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/*
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* FIXME:
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* We need CLK_IGNORE_UNUSED because mmc DT node point to xtal
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* instead of this clock. CCF would gate this on boot, killing
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* the mmc controller. Please remove this flag once DT properly
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* point to this clock instead of xtal
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*
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* Same goes for emmc B and C clocks
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*/
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.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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},
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};
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/* SDcard clock */
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static struct clk_mux gxbb_sd_emmc_b_clk0_sel = {
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.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
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.mask = 0x7,
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.shift = 25,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data) {
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.name = "sd_emmc_b_clk0_sel",
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.ops = &clk_mux_ops,
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.parent_names = gxbb_sd_emmc_clk0_parent_names,
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.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_divider gxbb_sd_emmc_b_clk0_div = {
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.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
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.shift = 16,
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.width = 7,
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.lock = &clk_lock,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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.hw.init = &(struct clk_init_data) {
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.name = "sd_emmc_b_clk0_div",
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.ops = &clk_divider_ops,
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.parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_gate gxbb_sd_emmc_b_clk0 = {
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.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
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.bit_idx = 23,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "sd_emmc_b_clk0",
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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},
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};
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/* EMMC/NAND clock */
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static struct clk_mux gxbb_sd_emmc_c_clk0_sel = {
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.reg = (void *)HHI_NAND_CLK_CNTL,
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.mask = 0x7,
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.shift = 9,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data) {
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.name = "sd_emmc_c_clk0_sel",
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.ops = &clk_mux_ops,
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.parent_names = gxbb_sd_emmc_clk0_parent_names,
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.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_divider gxbb_sd_emmc_c_clk0_div = {
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.reg = (void *)HHI_NAND_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.lock = &clk_lock,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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.hw.init = &(struct clk_init_data) {
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.name = "sd_emmc_c_clk0_div",
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.ops = &clk_divider_ops,
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.parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_gate gxbb_sd_emmc_c_clk0 = {
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.reg = (void *)HHI_NAND_CLK_CNTL,
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.bit_idx = 7,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "sd_emmc_c_clk0",
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.ops = &clk_gate_ops,
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.parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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},
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};
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/* Everything Else (EE) domain gates */
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static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
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static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
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@@ -1188,6 +1340,16 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
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[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
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[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
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[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
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[CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
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[CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
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[CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
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[CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
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[CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
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[CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
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[CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
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[CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
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[CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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};
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@@ -1310,6 +1472,16 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
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[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
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[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
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[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
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[CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
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[CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
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[CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
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[CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
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[CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
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[CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
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[CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
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[CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
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[CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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};
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@@ -1425,6 +1597,9 @@ static struct clk_gate *const gxbb_clk_gates[] = {
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&gxbb_cts_amclk,
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&gxbb_cts_mclk_i958,
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&gxbb_32k_clk,
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&gxbb_sd_emmc_a_clk0,
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&gxbb_sd_emmc_b_clk0,
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&gxbb_sd_emmc_c_clk0,
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};
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static struct clk_mux *const gxbb_clk_muxes[] = {
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@@ -1437,6 +1612,9 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
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&gxbb_cts_mclk_i958_sel,
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&gxbb_cts_i958,
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&gxbb_32k_clk_sel,
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&gxbb_sd_emmc_a_clk0_sel,
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&gxbb_sd_emmc_b_clk0_sel,
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&gxbb_sd_emmc_c_clk0_sel,
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};
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static struct clk_divider *const gxbb_clk_dividers[] = {
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@@ -1446,6 +1624,9 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
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&gxbb_mali_1_div,
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&gxbb_cts_mclk_i958_div,
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&gxbb_32k_clk_div,
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&gxbb_sd_emmc_a_clk0_div,
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&gxbb_sd_emmc_b_clk0_div,
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&gxbb_sd_emmc_c_clk0_div,
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};
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static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
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