xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

KVM: s390: gaccess: implement instruction fetching mode

Browse Source 
When an instruction is to be fetched, special handling applies to
secondary-space mode and access-register mode. The instruction is to be
fetched from primary space.

We can easily support this by selecting the right asce for translation.
Access registers will never be used during translation, so don't
include them in the interface. As we only want to read from the current
PSW address for now, let's also hide that detail.

Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
This commit is contained in:
David Hildenbrand
2015-11-16 15:48:59 +01:00
committed by Christian Borntraeger
parent 92c9632119
commit 34346b9a93
2 changed files with 28 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
arch/s390/kvm/gaccess.c
View File

@@ -480,22 +480,25 @@ static int get_vcpu_asce(struct kvm_vcpu *vcpu, union asce *asce,
ar_t ar, enum gacc_mode mode)
{
int rc;
psw_t *psw = &vcpu->arch.sie_block->gpsw;
struct psw_bits psw = psw_bits(vcpu->arch.sie_block->gpsw);
struct kvm_s390_pgm_info *pgm = &vcpu->arch.pgm;
struct trans_exc_code_bits *tec_bits;
memset(pgm, 0, sizeof(*pgm));
tec_bits = (struct trans_exc_code_bits *)&pgm->trans_exc_code;
tec_bits->fsi = mode == GACC_STORE ? FSI_STORE : FSI_FETCH;
tec_bits->as = psw_bits(*psw).as;
tec_bits->as = psw.as;
if (!psw_bits(*psw).t) {
if (!psw.t) {
asce->val = 0;
asce->r = 1;
return 0;
}
switch (psw_bits(vcpu->arch.sie_block->gpsw).as) {
if (mode == GACC_IFETCH)
psw.as = psw.as == PSW_AS_HOME ? PSW_AS_HOME : PSW_AS_PRIMARY;
switch (psw.as) {
case PSW_AS_PRIMARY:
asce->val = vcpu->arch.sie_block->gcr[1];
return 0;