Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Arnd Bergmann: "Newly added support for additional SoCs: - Axis Artpec-6 SoC family - Allwinner A83T SoC - Mediatek MT7623 - NXP i.MX6QP SoC - ST Microelectronics stm32f469 microcontroller New features: - SMP support for Mediatek mt2701 - Big-endian support for NXP i.MX - DaVinci now uses the new DMA engine dma_slave_map - OMAP now uses the new DMA engine dma_slave_map - earlyprintk support for palmchip uart on mach-tango - delay timer support for orion Other: - Exynos PMU driver moved out to drivers/soc/ - Various smaller updates for Renesas, Xilinx, PXA, AT91, OMAP, uniphier" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits) ARM: uniphier: rework SMP code to support new System Bus binding ARM: uniphier: add missing of_node_put() ARM: at91: avoid defining CONFIG_* symbols in source code ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1 ARM: imx: Make reset_control_ops const ARM: imx: Do L2 errata only if the L2 cache isn't enabled ARM: imx: select ARM_CPU_SUSPEND only for imx6 dmaengine: pxa_dma: fix the maximum requestor line ARM: alpine: select the Alpine MSI controller driver ARM: pxa: add the number of DMA requestor lines dmaengine: mmp-pdma: add number of requestors dma: mmp_pdma: Add the #dma-requests DT property documentation ARM: OMAP2+: Add rtc hwmod configuration for ti81xx ARM: s3c24xx: Avoid warning for inb/outb ARM: zynq: Move early printk virtual address to vmalloc area ARM: DRA7: hwmod: Add custom reset handler for PCIeSS ARM: SAMSUNG: Remove unused register offset definition ARM: EXYNOS: Cleanup header files inclusion drivers: soc: samsung: Enable COMPILE_TEST MAINTAINERS: Add maintainers entry for drivers/soc/samsung ...
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@@ -134,10 +134,10 @@
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/*
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* PXA2xx specific Core clock definitions
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*/
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#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
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#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
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#define CKEN __REG(0x41300004) /* Clock Enable Register */
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#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
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#define CCCR io_p2v(0x41300000) /* Core Clock Configuration Register */
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#define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */
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#define CKEN io_p2v(0x41300004) /* Clock Enable Register */
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#define OSCC io_p2v(0x41300008) /* Oscillator Configuration Register */
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#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
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#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
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@@ -18,7 +18,7 @@
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/*
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* Oscillator Configuration Register (OSCC)
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*/
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#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */
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#define OSCC io_p2v(0x41350000) /* Oscillator Configuration Register */
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#define OSCC_PEN (1 << 11) /* 13MHz POUT */
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