rt2x00: move under ralink vendor directory
Part of reorganising wireless drivers directory and Kconfig. Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
277
drivers/net/wireless/ralink/rt2x00/rt2x00reg.h
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277
drivers/net/wireless/ralink/rt2x00/rt2x00reg.h
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/*
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Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
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<http://rt2x00.serialmonkey.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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Module: rt2x00
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Abstract: rt2x00 generic register information.
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*/
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#ifndef RT2X00REG_H
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#define RT2X00REG_H
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/*
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* RX crypto status
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*/
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enum rx_crypto {
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RX_CRYPTO_SUCCESS = 0,
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RX_CRYPTO_FAIL_ICV = 1,
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RX_CRYPTO_FAIL_MIC = 2,
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RX_CRYPTO_FAIL_KEY = 3,
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};
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/*
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* Antenna values
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*/
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enum antenna {
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ANTENNA_SW_DIVERSITY = 0,
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ANTENNA_A = 1,
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ANTENNA_B = 2,
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ANTENNA_HW_DIVERSITY = 3,
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};
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/*
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* Led mode values.
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*/
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enum led_mode {
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LED_MODE_DEFAULT = 0,
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LED_MODE_TXRX_ACTIVITY = 1,
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LED_MODE_SIGNAL_STRENGTH = 2,
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LED_MODE_ASUS = 3,
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LED_MODE_ALPHA = 4,
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};
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/*
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* TSF sync values
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*/
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enum tsf_sync {
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TSF_SYNC_NONE = 0,
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TSF_SYNC_INFRA = 1,
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TSF_SYNC_ADHOC = 2,
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TSF_SYNC_AP_NONE = 3,
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};
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/*
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* Device states
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*/
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enum dev_state {
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STATE_DEEP_SLEEP = 0,
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STATE_SLEEP = 1,
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STATE_STANDBY = 2,
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STATE_AWAKE = 3,
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/*
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* Additional device states, these values are
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* not strict since they are not directly passed
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* into the device.
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*/
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STATE_RADIO_ON,
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STATE_RADIO_OFF,
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STATE_RADIO_IRQ_ON,
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STATE_RADIO_IRQ_OFF,
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};
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/*
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* IFS backoff values
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*/
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enum ifs {
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IFS_BACKOFF = 0,
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IFS_SIFS = 1,
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IFS_NEW_BACKOFF = 2,
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IFS_NONE = 3,
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};
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/*
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* IFS backoff values for HT devices
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*/
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enum txop {
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TXOP_HTTXOP = 0,
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TXOP_PIFS = 1,
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TXOP_SIFS = 2,
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TXOP_BACKOFF = 3,
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};
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/*
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* Cipher types for hardware encryption
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*/
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enum cipher {
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CIPHER_NONE = 0,
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CIPHER_WEP64 = 1,
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CIPHER_WEP128 = 2,
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CIPHER_TKIP = 3,
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CIPHER_AES = 4,
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/*
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* The following fields were added by rt61pci and rt73usb.
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*/
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CIPHER_CKIP64 = 5,
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CIPHER_CKIP128 = 6,
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CIPHER_TKIP_NO_MIC = 7, /* Don't send to device */
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/*
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* Max cipher type.
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* Note that CIPHER_NONE isn't counted, and CKIP64 and CKIP128
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* are excluded due to limitations in mac80211.
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*/
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CIPHER_MAX = 4,
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};
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/*
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* Rate modulations
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*/
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enum rate_modulation {
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RATE_MODE_CCK = 0,
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RATE_MODE_OFDM = 1,
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RATE_MODE_HT_MIX = 2,
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RATE_MODE_HT_GREENFIELD = 3,
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};
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/*
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* Firmware validation error codes
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*/
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enum firmware_errors {
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FW_OK,
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FW_BAD_CRC,
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FW_BAD_LENGTH,
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FW_BAD_VERSION,
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};
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/*
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* Register handlers.
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* We store the position of a register field inside a field structure,
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* This will simplify the process of setting and reading a certain field
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* inside the register while making sure the process remains byte order safe.
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*/
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struct rt2x00_field8 {
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u8 bit_offset;
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u8 bit_mask;
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};
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struct rt2x00_field16 {
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u16 bit_offset;
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u16 bit_mask;
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};
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struct rt2x00_field32 {
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u32 bit_offset;
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u32 bit_mask;
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};
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/*
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* Power of two check, this will check
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* if the mask that has been given contains and contiguous set of bits.
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* Note that we cannot use the is_power_of_2() function since this
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* check must be done at compile-time.
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*/
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#define is_power_of_two(x) ( !((x) & ((x)-1)) )
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#define low_bit_mask(x) ( ((x)-1) & ~(x) )
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#define is_valid_mask(x) is_power_of_two(1LU + (x) + low_bit_mask(x))
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/*
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* Macros to find first set bit in a variable.
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* These macros behave the same as the __ffs() functions but
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* the most important difference that this is done during
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* compile-time rather then run-time.
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*/
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#define compile_ffs2(__x) \
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__builtin_choose_expr(((__x) & 0x1), 0, 1)
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#define compile_ffs4(__x) \
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__builtin_choose_expr(((__x) & 0x3), \
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(compile_ffs2((__x))), \
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(compile_ffs2((__x) >> 2) + 2))
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#define compile_ffs8(__x) \
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__builtin_choose_expr(((__x) & 0xf), \
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(compile_ffs4((__x))), \
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(compile_ffs4((__x) >> 4) + 4))
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#define compile_ffs16(__x) \
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__builtin_choose_expr(((__x) & 0xff), \
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(compile_ffs8((__x))), \
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(compile_ffs8((__x) >> 8) + 8))
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#define compile_ffs32(__x) \
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__builtin_choose_expr(((__x) & 0xffff), \
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(compile_ffs16((__x))), \
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(compile_ffs16((__x) >> 16) + 16))
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/*
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* This macro will check the requirements for the FIELD{8,16,32} macros
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* The mask should be a constant non-zero contiguous set of bits which
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* does not exceed the given typelimit.
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*/
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#define FIELD_CHECK(__mask, __type) \
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BUILD_BUG_ON(!(__mask) || \
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!is_valid_mask(__mask) || \
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(__mask) != (__type)(__mask)) \
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#define FIELD8(__mask) \
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({ \
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FIELD_CHECK(__mask, u8); \
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(struct rt2x00_field8) { \
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compile_ffs8(__mask), (__mask) \
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}; \
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})
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#define FIELD16(__mask) \
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({ \
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FIELD_CHECK(__mask, u16); \
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(struct rt2x00_field16) { \
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compile_ffs16(__mask), (__mask) \
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}; \
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})
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#define FIELD32(__mask) \
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({ \
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FIELD_CHECK(__mask, u32); \
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(struct rt2x00_field32) { \
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compile_ffs32(__mask), (__mask) \
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}; \
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})
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#define SET_FIELD(__reg, __type, __field, __value)\
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({ \
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typecheck(__type, __field); \
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*(__reg) &= ~((__field).bit_mask); \
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*(__reg) |= ((__value) << \
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((__field).bit_offset)) & \
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((__field).bit_mask); \
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})
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#define GET_FIELD(__reg, __type, __field) \
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({ \
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typecheck(__type, __field); \
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((__reg) & ((__field).bit_mask)) >> \
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((__field).bit_offset); \
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})
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#define rt2x00_set_field32(__reg, __field, __value) \
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SET_FIELD(__reg, struct rt2x00_field32, __field, __value)
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#define rt2x00_get_field32(__reg, __field) \
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GET_FIELD(__reg, struct rt2x00_field32, __field)
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#define rt2x00_set_field16(__reg, __field, __value) \
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SET_FIELD(__reg, struct rt2x00_field16, __field, __value)
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#define rt2x00_get_field16(__reg, __field) \
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GET_FIELD(__reg, struct rt2x00_field16, __field)
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#define rt2x00_set_field8(__reg, __field, __value) \
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SET_FIELD(__reg, struct rt2x00_field8, __field, __value)
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#define rt2x00_get_field8(__reg, __field) \
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GET_FIELD(__reg, struct rt2x00_field8, __field)
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#endif /* RT2X00REG_H */
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