Merge tag 'tty-4.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

Pull tty/serial driver updates from Greg KH:
 "Here is the big tty and serial driver pull request for 4.19-rc1.

  It's not all that big, just a number of small serial driver updates
  and fixes, along with some better vt handling for unicode characters
  for those using braille terminals.

  All of these patches have been in linux-next for a long time with no
  reported issues"

* tag 'tty-4.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (73 commits)
  tty: serial: 8250: Revert NXP SC16C2552 workaround
  serial: 8250_exar: Read INT0 from slave device, too
  tty: rocket: Fix possible buffer overwrite on register_PCI
  serial: 8250_dw: Add ACPI support for uart on Broadcom SoC
  serial: 8250_dw: always set baud rate in dw8250_set_termios
  dt-bindings: serial: Add binding for uartlite
  tty: serial: uartlite: Add support for suspend and resume
  tty: serial: uartlite: Add clock adaptation
  tty: serial: uartlite: Add structure for private data
  serial: sh-sci: Improve support for separate TEI and DRI interrupts
  serial: sh-sci: Remove SCIx_RZ_SCIFA_REGTYPE
  serial: sh-sci: Allow for compressed SCIF address
  serial: sh-sci: Improve interrupts description
  serial: 8250: Use cached port name directly in messages
  serial: 8250_exar: Drop unused variable in pci_xr17v35x_setup()
  vt: drop unused struct vt_struct
  vt: avoid a VLA in the unicode screen scroll function
  vt: add /dev/vcsu* to devices.txt
  vt: coherence validation code for the unicode screen buffer
  vt: selection: take screen contents from uniscr if available
  ...
This commit is contained in:
Linus Torvalds
2018-08-18 10:50:41 -07:00
44 changed files with 1382 additions and 339 deletions

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@@ -11,6 +11,7 @@ compatible: Must contain one of
"mediatek,mt6589"
"mediatek,mt6592"
"mediatek,mt6755"
"mediatek,mt6765"
"mediatek,mt6795"
"mediatek,mt6797"
"mediatek,mt7622"
@@ -41,6 +42,9 @@ Supported boards:
- Evaluation phone for MT6755(Helio P10):
Required root node properties:
- compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
- Evaluation board for MT6765(Helio P22):
Required root node properties:
- compatible = "mediatek,mt6765-evb", "mediatek,mt6765";
- Evaluation board for MT6795(Helio X10):
Required root node properties:
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";

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@@ -11,6 +11,7 @@ Required properties:
"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
"mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765
"mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
"mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
"mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589

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@@ -9,7 +9,11 @@ Optional properties:
- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
in DCE mode by default.
- rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
linux,rs485-enabled-at-boot-time: see rs485.txt
linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485
you must enable either the "uart-has-rtscts" or the "rts-gpios"
properties. In case you use "uart-has-rtscts" the signal that controls
the transceiver is actually CTS_B, not RTS_B. CTS_B is always output,
and RTS_B is input, regardless of dte-mode.
Please check Documentation/devicetree/bindings/serial/serial.txt
for the complete list of generic properties.

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@@ -8,6 +8,7 @@ Required properties:
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
* "mediatek,mt6755-uart" for MT6755 compatible UARTS
* "mediatek,mt6765-uart" for MT6765 compatible UARTS
* "mediatek,mt6795-uart" for MT6795 compatible UARTS
* "mediatek,mt6797-uart" for MT6797 compatible UARTS
* "mediatek,mt7622-uart" for MT7622 compatible UARTS

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@@ -1,6 +1,7 @@
OMAP UART controller
Required properties:
- compatible : should be "ti,am654-uart" for AM654 controllers
- compatible : should be "ti,omap2-uart" for OMAP2 controllers
- compatible : should be "ti,omap3-uart" for OMAP3 controllers
- compatible : should be "ti,omap4-uart" for OMAP4 controllers

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@@ -0,0 +1,10 @@
Renesas RZ/N1 UART
This controller is based on the Synopsys DesignWare ABP UART and inherits all
properties defined in snps-dw-apb-uart.txt except for the compatible property.
Required properties:
- compatible : The device specific string followed by the generic RZ/N1 string.
Therefore it must be one of:
"renesas,r9a06g032-uart", "renesas,rzn1-uart"
"renesas,r9a06g033-uart", "renesas,rzn1-uart"

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@@ -5,6 +5,7 @@ Required properties:
- compatible: Must contain one or more of the following:
- "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART.
- "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART.
- "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART.
- "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
- "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
@@ -72,7 +73,21 @@ Required properties:
family-specific and/or generic versions.
- reg: Base address and length of the I/O registers used by the UART.
- interrupts: Must contain an interrupt-specifier for the SCIx interrupt.
- interrupts: Must contain one or more interrupt-specifiers for the SCIx.
If a single interrupt is expressed, then all events are
multiplexed into this single interrupt.
If multiple interrupts are provided by the hardware, the order
in which the interrupts are listed must match order below. Note
that some HW interrupt events may be muxed together resulting
in duplicate entries.
The interrupt order is as follows:
1. Error (ERI)
2. Receive buffer full (RXI)
3. Transmit buffer empty (TXI)
4. Break (BRI)
5. Data Ready (DRI)
6. Transmit End (TEI)
- clocks: Must contain a phandle and clock-specifier pair for each entry
in clock-names.
@@ -89,7 +104,7 @@ Required properties:
- "scif_clk" for the optional external clock source for the frequency
divider (SCIF_CLK).
Note: Each enabled SCIx UART should have an alias correctly numbered in the
Note: Each enabled SCIx UART may have an optional "serialN" alias in the
"aliases" node.
Optional properties:

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@@ -0,0 +1,23 @@
Xilinx Axi Uartlite controller Device Tree Bindings
---------------------------------------------------------
Required properties:
- compatible : Can be either of
"xlnx,xps-uartlite-1.00.a"
"xlnx,opb-uartlite-1.00.b"
- reg : Physical base address and size of the Axi Uartlite
registers map.
- interrupts : Should contain the UART controller interrupt.
Optional properties:
- port-number : Set Uart port number
- clock-names : Should be "s_axi_aclk"
- clocks : Input clock specifier. Refer to common clock bindings.
Example:
serial@800c0000 {
compatible = "xlnx,xps-uartlite-1.00.a";
reg = <0x0 0x800c0000 0x10000>;
interrupts = <0x0 0x6e 0x1>;
port-number = <0>;
};

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@@ -46,7 +46,7 @@ Child nodes should conform to I2C bus binding as described in i2c.txt.
Qualcomm Technologies Inc. GENI Serial Engine based UART Controller
Required properties:
- compatible: Must be "qcom,geni-debug-uart".
- compatible: Must be "qcom,geni-debug-uart" or "qcom,geni-uart".
- reg: Must contain UART register location and length.
- interrupts: Must contain UART core interrupts.
- clock-names: Must contain "se".