Merge tag 'tty-4.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
Pull tty/serial driver updates from Greg KH: "Here is the big tty and serial driver pull request for 4.19-rc1. It's not all that big, just a number of small serial driver updates and fixes, along with some better vt handling for unicode characters for those using braille terminals. All of these patches have been in linux-next for a long time with no reported issues" * tag 'tty-4.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (73 commits) tty: serial: 8250: Revert NXP SC16C2552 workaround serial: 8250_exar: Read INT0 from slave device, too tty: rocket: Fix possible buffer overwrite on register_PCI serial: 8250_dw: Add ACPI support for uart on Broadcom SoC serial: 8250_dw: always set baud rate in dw8250_set_termios dt-bindings: serial: Add binding for uartlite tty: serial: uartlite: Add support for suspend and resume tty: serial: uartlite: Add clock adaptation tty: serial: uartlite: Add structure for private data serial: sh-sci: Improve support for separate TEI and DRI interrupts serial: sh-sci: Remove SCIx_RZ_SCIFA_REGTYPE serial: sh-sci: Allow for compressed SCIF address serial: sh-sci: Improve interrupts description serial: 8250: Use cached port name directly in messages serial: 8250_exar: Drop unused variable in pci_xr17v35x_setup() vt: drop unused struct vt_struct vt: avoid a VLA in the unicode screen scroll function vt: add /dev/vcsu* to devices.txt vt: coherence validation code for the unicode screen buffer vt: selection: take screen contents from uniscr if available ...
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@@ -11,6 +11,7 @@ compatible: Must contain one of
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"mediatek,mt6589"
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"mediatek,mt6592"
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"mediatek,mt6755"
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"mediatek,mt6765"
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"mediatek,mt6795"
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"mediatek,mt6797"
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"mediatek,mt7622"
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@@ -41,6 +42,9 @@ Supported boards:
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- Evaluation phone for MT6755(Helio P10):
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Required root node properties:
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- compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
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- Evaluation board for MT6765(Helio P22):
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Required root node properties:
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- compatible = "mediatek,mt6765-evb", "mediatek,mt6765";
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- Evaluation board for MT6795(Helio X10):
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Required root node properties:
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- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
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@@ -11,6 +11,7 @@ Required properties:
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"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
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"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
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"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
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"mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765
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"mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
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"mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
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"mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589
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@@ -9,7 +9,11 @@ Optional properties:
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- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
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in DCE mode by default.
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- rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
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linux,rs485-enabled-at-boot-time: see rs485.txt
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linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485
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you must enable either the "uart-has-rtscts" or the "rts-gpios"
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properties. In case you use "uart-has-rtscts" the signal that controls
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the transceiver is actually CTS_B, not RTS_B. CTS_B is always output,
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and RTS_B is input, regardless of dte-mode.
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Please check Documentation/devicetree/bindings/serial/serial.txt
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for the complete list of generic properties.
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@@ -8,6 +8,7 @@ Required properties:
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* "mediatek,mt6582-uart" for MT6582 compatible UARTS
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* "mediatek,mt6589-uart" for MT6589 compatible UARTS
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* "mediatek,mt6755-uart" for MT6755 compatible UARTS
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* "mediatek,mt6765-uart" for MT6765 compatible UARTS
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* "mediatek,mt6795-uart" for MT6795 compatible UARTS
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* "mediatek,mt6797-uart" for MT6797 compatible UARTS
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* "mediatek,mt7622-uart" for MT7622 compatible UARTS
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@@ -1,6 +1,7 @@
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OMAP UART controller
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Required properties:
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- compatible : should be "ti,am654-uart" for AM654 controllers
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- compatible : should be "ti,omap2-uart" for OMAP2 controllers
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- compatible : should be "ti,omap3-uart" for OMAP3 controllers
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- compatible : should be "ti,omap4-uart" for OMAP4 controllers
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@@ -0,0 +1,10 @@
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Renesas RZ/N1 UART
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This controller is based on the Synopsys DesignWare ABP UART and inherits all
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properties defined in snps-dw-apb-uart.txt except for the compatible property.
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Required properties:
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- compatible : The device specific string followed by the generic RZ/N1 string.
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Therefore it must be one of:
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"renesas,r9a06g032-uart", "renesas,rzn1-uart"
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"renesas,r9a06g033-uart", "renesas,rzn1-uart"
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@@ -5,6 +5,7 @@ Required properties:
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- compatible: Must contain one or more of the following:
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- "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART.
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- "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART.
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- "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART.
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- "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
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- "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
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@@ -72,7 +73,21 @@ Required properties:
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family-specific and/or generic versions.
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- reg: Base address and length of the I/O registers used by the UART.
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- interrupts: Must contain an interrupt-specifier for the SCIx interrupt.
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- interrupts: Must contain one or more interrupt-specifiers for the SCIx.
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If a single interrupt is expressed, then all events are
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multiplexed into this single interrupt.
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If multiple interrupts are provided by the hardware, the order
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in which the interrupts are listed must match order below. Note
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that some HW interrupt events may be muxed together resulting
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in duplicate entries.
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The interrupt order is as follows:
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1. Error (ERI)
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2. Receive buffer full (RXI)
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3. Transmit buffer empty (TXI)
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4. Break (BRI)
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5. Data Ready (DRI)
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6. Transmit End (TEI)
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- clocks: Must contain a phandle and clock-specifier pair for each entry
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in clock-names.
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@@ -89,7 +104,7 @@ Required properties:
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- "scif_clk" for the optional external clock source for the frequency
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divider (SCIF_CLK).
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Note: Each enabled SCIx UART should have an alias correctly numbered in the
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Note: Each enabled SCIx UART may have an optional "serialN" alias in the
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"aliases" node.
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Optional properties:
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@@ -0,0 +1,23 @@
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Xilinx Axi Uartlite controller Device Tree Bindings
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---------------------------------------------------------
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Required properties:
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- compatible : Can be either of
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"xlnx,xps-uartlite-1.00.a"
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"xlnx,opb-uartlite-1.00.b"
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- reg : Physical base address and size of the Axi Uartlite
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registers map.
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- interrupts : Should contain the UART controller interrupt.
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Optional properties:
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- port-number : Set Uart port number
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- clock-names : Should be "s_axi_aclk"
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- clocks : Input clock specifier. Refer to common clock bindings.
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Example:
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serial@800c0000 {
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compatible = "xlnx,xps-uartlite-1.00.a";
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reg = <0x0 0x800c0000 0x10000>;
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interrupts = <0x0 0x6e 0x1>;
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port-number = <0>;
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};
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@@ -46,7 +46,7 @@ Child nodes should conform to I2C bus binding as described in i2c.txt.
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Qualcomm Technologies Inc. GENI Serial Engine based UART Controller
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Required properties:
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- compatible: Must be "qcom,geni-debug-uart".
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- compatible: Must be "qcom,geni-debug-uart" or "qcom,geni-uart".
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- reg: Must contain UART register location and length.
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- interrupts: Must contain UART core interrupts.
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- clock-names: Must contain "se".
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