Merge tag 'tegra-for-3.7-dmaengine' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/cleanup
ARM: tegra: switch to dmaengine The Tegra code-base has contained both a legacy DMA and a dmaengine driver since v3.6-rcX. This series flips Tegra's defconfig to enable dmaengine rather than the legacy driver, and removes the legacy driver and all client code. * tag 'tegra-for-3.7-dmaengine' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ASoC: tegra: remove support of legacy DMA driver based access spi: tegra: remove support of legacy DMA driver based access ARM: tegra: apbio: remove support of legacy DMA driver based access ARM: tegra: dma: remove legacy APB DMA driver ARM: tegra: config: enable dmaengine based APB DMA driver + sync to 3.6-rc6
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@@ -159,6 +159,12 @@ static int debug_arch_supported(void)
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arch >= ARM_DEBUG_ARCH_V7_1;
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}
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/* Can we determine the watchpoint access type from the fsr? */
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static int debug_exception_updates_fsr(void)
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{
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return 0;
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}
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/* Determine number of WRP registers available. */
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static int get_num_wrp_resources(void)
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{
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@@ -604,13 +610,14 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
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/* Aligned */
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break;
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case 1:
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/* Allow single byte watchpoint. */
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if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
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break;
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case 2:
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/* Allow halfword watchpoints and breakpoints. */
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if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
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break;
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case 3:
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/* Allow single byte watchpoint. */
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if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
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break;
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default:
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ret = -EINVAL;
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goto out;
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@@ -619,18 +626,35 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
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info->address &= ~alignment_mask;
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info->ctrl.len <<= offset;
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/*
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* Currently we rely on an overflow handler to take
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* care of single-stepping the breakpoint when it fires.
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* In the case of userspace breakpoints on a core with V7 debug,
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* we can use the mismatch feature as a poor-man's hardware
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* single-step, but this only works for per-task breakpoints.
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*/
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if (!bp->overflow_handler && (arch_check_bp_in_kernelspace(bp) ||
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!core_has_mismatch_brps() || !bp->hw.bp_target)) {
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pr_warning("overflow handler required but none found\n");
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ret = -EINVAL;
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if (!bp->overflow_handler) {
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/*
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* Mismatch breakpoints are required for single-stepping
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* breakpoints.
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*/
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if (!core_has_mismatch_brps())
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return -EINVAL;
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/* We don't allow mismatch breakpoints in kernel space. */
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if (arch_check_bp_in_kernelspace(bp))
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return -EPERM;
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/*
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* Per-cpu breakpoints are not supported by our stepping
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* mechanism.
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*/
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if (!bp->hw.bp_target)
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return -EINVAL;
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/*
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* We only support specific access types if the fsr
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* reports them.
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*/
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if (!debug_exception_updates_fsr() &&
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(info->ctrl.type == ARM_BREAKPOINT_LOAD ||
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info->ctrl.type == ARM_BREAKPOINT_STORE))
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return -EINVAL;
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}
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out:
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return ret;
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}
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@@ -706,10 +730,12 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr,
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goto unlock;
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/* Check that the access type matches. */
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access = (fsr & ARM_FSR_ACCESS_MASK) ? HW_BREAKPOINT_W :
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HW_BREAKPOINT_R;
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if (!(access & hw_breakpoint_type(wp)))
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goto unlock;
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if (debug_exception_updates_fsr()) {
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access = (fsr & ARM_FSR_ACCESS_MASK) ?
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HW_BREAKPOINT_W : HW_BREAKPOINT_R;
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if (!(access & hw_breakpoint_type(wp)))
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goto unlock;
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}
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/* We have a winner. */
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info->trigger = addr;
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@@ -420,20 +420,23 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
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#endif
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instr = *(u32 *) pc;
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} else if (thumb_mode(regs)) {
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get_user(instr, (u16 __user *)pc);
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if (get_user(instr, (u16 __user *)pc))
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goto die_sig;
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if (is_wide_instruction(instr)) {
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unsigned int instr2;
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get_user(instr2, (u16 __user *)pc+1);
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if (get_user(instr2, (u16 __user *)pc+1))
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goto die_sig;
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instr <<= 16;
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instr |= instr2;
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}
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} else {
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get_user(instr, (u32 __user *)pc);
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} else if (get_user(instr, (u32 __user *)pc)) {
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goto die_sig;
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}
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if (call_undef_hook(regs, instr) == 0)
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return;
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die_sig:
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#ifdef CONFIG_DEBUG_USER
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if (user_debug & UDBG_UNDEFINED) {
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printk(KERN_INFO "%s (%d): undefined instruction: pc=%p\n",
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