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perf/x86/amd: Cleanup Fam10h NB event constraints

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Avoid allocating the AMD NB event constraints data structure when not
needed. This gets rid of x86_max_cores usage and avoids allocating
this on AMD Core Perfctr supporting hardware (which has separate MSRs
for NB events).

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: aherrmann@suse.com
Cc: Rui Huang <ray.huang@amd.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: jencce.kernel@gmail.com
Link: http://lkml.kernel.org/r/20160320124629.GY6375@twins.programming.kicks-ass.net
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Peter Zijlstra
2016-03-25 15:52:35 +01:00
committed by Thomas Gleixner
parent ee6825c80e
commit 32b62f4468
2 changed files with 23 additions and 3 deletions
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5
arch/x86/events/perf_event.h
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@@ -607,6 +607,11 @@ struct x86_pmu {
*/
atomic_t lbr_exclusive[x86_lbr_exclusive_max];
/*
* AMD bits
*/
unsigned int amd_nb_constraints : 1;
/*
* Extra registers for events
*/