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powerpc: Use instruction emulation infrastructure to handle alignment faults

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This replaces almost all of the instruction emulation code in
fix_alignment() with calls to analyse_instr(), emulate_loadstore()
and emulate_dcbz().  The only emulation code left is the SPE
emulation code; analyse_instr() etc. do not handle SPE instructions
at present.

One result of this is that we can now handle alignment faults on
all the new VSX load and store instructions that were added in POWER9.
VSX loads/stores will take alignment faults for unaligned accesses
to cache-inhibited memory.

Another effect is that we no longer rely on the DAR and DSISR values
set by the processor.

With this, we now need to include the instruction emulation code
unconditionally.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Paul Mackerras
2017-08-30 14:12:40 +10:00
committed by Michael Ellerman
parent a53d5182e2
commit 31bfdb036f
3 changed files with 34 additions and 777 deletions
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4
arch/powerpc/lib/Makefile
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@@ -31,8 +31,8 @@ obj64-$(CONFIG_KPROBES_SANITY_TEST) += test_emulate_step.o
obj-y += checksum_$(BITS).o checksum_wrappers.o
obj-$(CONFIG_PPC_EMULATE_SSTEP) += sstep.o ldstfp.o
obj64-$(CONFIG_PPC_EMULATE_SSTEP) += quad.o
obj-y += sstep.o ldstfp.o quad.o
obj64-y += quad.o
obj-$(CONFIG_PPC_LIB_RHEAP) += rheap.o