Merge tag 'sunxi-h3-h5-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

Allwinner H3/H5 changes for 4.19

Our usual bunch of changes shared between arm and arm64.

This time, we have:
  - eMMC support for the ALL-H3-CC boards
  - EMAC support for the Beelink X2

* tag 'sunxi-h3-h5-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  ARM: dts: sunxi-h3-h5: Remove unused address-cells/size-cells of dwmac-sun8i
  ARM: dts: sunxi: libretech-all-h3-cc: Enable eMMC module
  ARM: sun8i: h3: add SY8113B regulator on Banana Pi M2 Zero board
  ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2
  ARM: dts: sun8i-h3: Add missing cooling device properties for CPUs

Signed-off-by: Olof Johansson <olof@lixom.net>

arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts

@@ -48,6 +48,23 @@
 		};
 	};
 
+	reg_vdd_cpux: vdd-cpux-regulator {
+		compatible = "regulator-gpio";
+		regulator-name = "vdd-cpux";
+		regulator-type = "voltage";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-ramp-delay = <50>; /* 4ms */
+
+		gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
+		enable-active-high;
+		gpios-states = <0x1>;
+		states = <1100000 0x0
+			  1300000 0x1>;
+	};
+
 	wifi_pwrseq: wifi_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		pinctrl-names = "default";
@@ -55,6 +72,10 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&reg_vdd_cpux>;
+};
+
 &ehci0 {
 	status = "okay";
 };

arch/arm/boot/dts/sun8i-h3-beelink-x2.dts

@@ -123,6 +123,13 @@
 	status = "okay";
 };
 
+&emac {
+	phy-handle = <&int_mii_phy>;
+	phy-mode = "mii";
+	allwinner,leds-active-low;
+	status = "okay";
+};
+
 &hdmi {
 	status = "okay";
 };

arch/arm/boot/dts/sun8i-h3.dtsi

@@ -84,21 +84,30 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <1>;
+			clocks = <&ccu CLK_CPUX>;
+			clock-names = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu@2 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <2>;
+			clocks = <&ccu CLK_CPUX>;
+			clock-names = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu@3 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <3>;
+			clocks = <&ccu CLK_CPUX>;
+			clock-names = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>;
 		};
 	};
 

arch/arm/boot/dts/sunxi-h3-h5.dtsi

@@ -506,8 +506,6 @@
 			reset-names = "stmmaceth";
 			clocks = <&ccu CLK_BUS_EMAC>;
 			clock-names = "stmmaceth";
-			#address-cells = <1>;
-			#size-cells = <0>;
 			status = "disabled";
 
 			mdio: mdio {

arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi

@@ -178,6 +178,15 @@
 	status = "okay";
 };
 
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_8bit_pins>;
+	vmmc-supply = <&reg_vcc_io>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
 &ohci0 {
 	status = "okay";
 };