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Merge tag 'v3.13-rc1' into asoc-arizona

Browse Source 
Linux 3.13-rc1
This commit is contained in:
Mark Brown
2013-11-24 14:35:18 +00:00
parent 16ec790938 6ce4eac1f6
commit 30c27abd28
9123 changed files with 384454 additions and 191088 deletions
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2
include/linux/mfd/arizona/registers.h
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@@ -1942,7 +1942,7 @@
#define ARIZONA_FLL2_SYNC_GAIN_MASK 0x003c /* FLL2_SYNC_GAIN */
#define ARIZONA_FLL2_SYNC_GAIN_SHIFT 2 /* FLL2_SYNC_GAIN */
#define ARIZONA_FLL2_SYNC_GAIN_WIDTH 4 /* FLL2_SYNC_GAIN */
#define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */
#define ARIZONA_FLL2_SYNC_BW 0x0001 /* FLL2_SYNC_BW */
#define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */
#define ARIZONA_FLL2_SYNC_BW_SHIFT 0 /* FLL2_SYNC_BW */
#define ARIZONA_FLL2_SYNC_BW_WIDTH 1 /* FLL2_SYNC_BW */

423
include/linux/mfd/as3722.h Normal file
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@@ -0,0 +1,423 @@
/*
* as3722 definitions
*
* Copyright (C) 2013 ams
* Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
*
* Author: Florian Lobmaier <florian.lobmaier@ams.com>
* Author: Laxman Dewangan <ldewangan@nvidia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __LINUX_MFD_AS3722_H__
#define __LINUX_MFD_AS3722_H__
#include <linux/regmap.h>
/* AS3722 registers */
#define AS3722_SD0_VOLTAGE_REG 0x00
#define AS3722_SD1_VOLTAGE_REG 0x01
#define AS3722_SD2_VOLTAGE_REG 0x02
#define AS3722_SD3_VOLTAGE_REG 0x03
#define AS3722_SD4_VOLTAGE_REG 0x04
#define AS3722_SD5_VOLTAGE_REG 0x05
#define AS3722_SD6_VOLTAGE_REG 0x06
#define AS3722_GPIO0_CONTROL_REG 0x08
#define AS3722_GPIO1_CONTROL_REG 0x09
#define AS3722_GPIO2_CONTROL_REG 0x0A
#define AS3722_GPIO3_CONTROL_REG 0x0B
#define AS3722_GPIO4_CONTROL_REG 0x0C
#define AS3722_GPIO5_CONTROL_REG 0x0D
#define AS3722_GPIO6_CONTROL_REG 0x0E
#define AS3722_GPIO7_CONTROL_REG 0x0F
#define AS3722_LDO0_VOLTAGE_REG 0x10
#define AS3722_LDO1_VOLTAGE_REG 0x11
#define AS3722_LDO2_VOLTAGE_REG 0x12
#define AS3722_LDO3_VOLTAGE_REG 0x13
#define AS3722_LDO4_VOLTAGE_REG 0x14
#define AS3722_LDO5_VOLTAGE_REG 0x15
#define AS3722_LDO6_VOLTAGE_REG 0x16
#define AS3722_LDO7_VOLTAGE_REG 0x17
#define AS3722_LDO9_VOLTAGE_REG 0x19
#define AS3722_LDO10_VOLTAGE_REG 0x1A
#define AS3722_LDO11_VOLTAGE_REG 0x1B
#define AS3722_GPIO_DEB1_REG 0x1E
#define AS3722_GPIO_DEB2_REG 0x1F
#define AS3722_GPIO_SIGNAL_OUT_REG 0x20
#define AS3722_GPIO_SIGNAL_IN_REG 0x21
#define AS3722_REG_SEQU_MOD1_REG 0x22
#define AS3722_REG_SEQU_MOD2_REG 0x23
#define AS3722_REG_SEQU_MOD3_REG 0x24
#define AS3722_SD_PHSW_CTRL_REG 0x27
#define AS3722_SD_PHSW_STATUS 0x28
#define AS3722_SD0_CONTROL_REG 0x29
#define AS3722_SD1_CONTROL_REG 0x2A
#define AS3722_SDmph_CONTROL_REG 0x2B
#define AS3722_SD23_CONTROL_REG 0x2C
#define AS3722_SD4_CONTROL_REG 0x2D
#define AS3722_SD5_CONTROL_REG 0x2E
#define AS3722_SD6_CONTROL_REG 0x2F
#define AS3722_SD_DVM_REG 0x30
#define AS3722_RESET_REASON_REG 0x31
#define AS3722_BATTERY_VOLTAGE_MONITOR_REG 0x32
#define AS3722_STARTUP_CONTROL_REG 0x33
#define AS3722_RESET_TIMER_REG 0x34
#define AS3722_REFERENCE_CONTROL_REG 0x35
#define AS3722_RESET_CONTROL_REG 0x36
#define AS3722_OVER_TEMP_CONTROL_REG 0x37
#define AS3722_WATCHDOG_CONTROL_REG 0x38
#define AS3722_REG_STANDBY_MOD1_REG 0x39
#define AS3722_REG_STANDBY_MOD2_REG 0x3A
#define AS3722_REG_STANDBY_MOD3_REG 0x3B
#define AS3722_ENABLE_CTRL1_REG 0x3C
#define AS3722_ENABLE_CTRL2_REG 0x3D
#define AS3722_ENABLE_CTRL3_REG 0x3E
#define AS3722_ENABLE_CTRL4_REG 0x3F
#define AS3722_ENABLE_CTRL5_REG 0x40
#define AS3722_PWM_CONTROL_L_REG 0x41
#define AS3722_PWM_CONTROL_H_REG 0x42
#define AS3722_WATCHDOG_TIMER_REG 0x46
#define AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG 0x48
#define AS3722_IOVOLTAGE_REG 0x49
#define AS3722_BATTERY_VOLTAGE_MONITOR2_REG 0x4A
#define AS3722_SD_CONTROL_REG 0x4D
#define AS3722_LDOCONTROL0_REG 0x4E
#define AS3722_LDOCONTROL1_REG 0x4F
#define AS3722_SD0_PROTECT_REG 0x50
#define AS3722_SD6_PROTECT_REG 0x51
#define AS3722_PWM_VCONTROL1_REG 0x52
#define AS3722_PWM_VCONTROL2_REG 0x53
#define AS3722_PWM_VCONTROL3_REG 0x54
#define AS3722_PWM_VCONTROL4_REG 0x55
#define AS3722_BB_CHARGER_REG 0x57
#define AS3722_CTRL_SEQU1_REG 0x58
#define AS3722_CTRL_SEQU2_REG 0x59
#define AS3722_OVCURRENT_REG 0x5A
#define AS3722_OVCURRENT_DEB_REG 0x5B
#define AS3722_SDLV_DEB_REG 0x5C
#define AS3722_OC_PG_CTRL_REG 0x5D
#define AS3722_OC_PG_CTRL2_REG 0x5E
#define AS3722_CTRL_STATUS 0x5F
#define AS3722_RTC_CONTROL_REG 0x60
#define AS3722_RTC_SECOND_REG 0x61
#define AS3722_RTC_MINUTE_REG 0x62
#define AS3722_RTC_HOUR_REG 0x63
#define AS3722_RTC_DAY_REG 0x64
#define AS3722_RTC_MONTH_REG 0x65
#define AS3722_RTC_YEAR_REG 0x66
#define AS3722_RTC_ALARM_SECOND_REG 0x67
#define AS3722_RTC_ALARM_MINUTE_REG 0x68
#define AS3722_RTC_ALARM_HOUR_REG 0x69
#define AS3722_RTC_ALARM_DAY_REG 0x6A
#define AS3722_RTC_ALARM_MONTH_REG 0x6B
#define AS3722_RTC_ALARM_YEAR_REG 0x6C
#define AS3722_SRAM_REG 0x6D
#define AS3722_RTC_ACCESS_REG 0x6F
#define AS3722_RTC_STATUS_REG 0x73
#define AS3722_INTERRUPT_MASK1_REG 0x74
#define AS3722_INTERRUPT_MASK2_REG 0x75
#define AS3722_INTERRUPT_MASK3_REG 0x76
#define AS3722_INTERRUPT_MASK4_REG 0x77
#define AS3722_INTERRUPT_STATUS1_REG 0x78
#define AS3722_INTERRUPT_STATUS2_REG 0x79
#define AS3722_INTERRUPT_STATUS3_REG 0x7A
#define AS3722_INTERRUPT_STATUS4_REG 0x7B
#define AS3722_TEMP_STATUS_REG 0x7D
#define AS3722_ADC0_CONTROL_REG 0x80
#define AS3722_ADC1_CONTROL_REG 0x81
#define AS3722_ADC0_MSB_RESULT_REG 0x82
#define AS3722_ADC0_LSB_RESULT_REG 0x83
#define AS3722_ADC1_MSB_RESULT_REG 0x84
#define AS3722_ADC1_LSB_RESULT_REG 0x85
#define AS3722_ADC1_THRESHOLD_HI_MSB_REG 0x86
#define AS3722_ADC1_THRESHOLD_HI_LSB_REG 0x87
#define AS3722_ADC1_THRESHOLD_LO_MSB_REG 0x88
#define AS3722_ADC1_THRESHOLD_LO_LSB_REG 0x89
#define AS3722_ADC_CONFIGURATION_REG 0x8A
#define AS3722_ASIC_ID1_REG 0x90
#define AS3722_ASIC_ID2_REG 0x91
#define AS3722_LOCK_REG 0x9E
#define AS3722_MAX_REGISTER 0xF4
#define AS3722_SD0_EXT_ENABLE_MASK 0x03
#define AS3722_SD1_EXT_ENABLE_MASK 0x0C
#define AS3722_SD2_EXT_ENABLE_MASK 0x30
#define AS3722_SD3_EXT_ENABLE_MASK 0xC0
#define AS3722_SD4_EXT_ENABLE_MASK 0x03
#define AS3722_SD5_EXT_ENABLE_MASK 0x0C
#define AS3722_SD6_EXT_ENABLE_MASK 0x30
#define AS3722_LDO0_EXT_ENABLE_MASK 0x03
#define AS3722_LDO1_EXT_ENABLE_MASK 0x0C
#define AS3722_LDO2_EXT_ENABLE_MASK 0x30
#define AS3722_LDO3_EXT_ENABLE_MASK 0xC0
#define AS3722_LDO4_EXT_ENABLE_MASK 0x03
#define AS3722_LDO5_EXT_ENABLE_MASK 0x0C
#define AS3722_LDO6_EXT_ENABLE_MASK 0x30
#define AS3722_LDO7_EXT_ENABLE_MASK 0xC0
#define AS3722_LDO9_EXT_ENABLE_MASK 0x0C
#define AS3722_LDO10_EXT_ENABLE_MASK 0x30
#define AS3722_LDO11_EXT_ENABLE_MASK 0xC0
#define AS3722_OVCURRENT_SD0_ALARM_MASK 0x07
#define AS3722_OVCURRENT_SD0_ALARM_SHIFT 0x01
#define AS3722_OVCURRENT_SD0_TRIP_MASK 0x18
#define AS3722_OVCURRENT_SD0_TRIP_SHIFT 0x03
#define AS3722_OVCURRENT_SD1_TRIP_MASK 0x60
#define AS3722_OVCURRENT_SD1_TRIP_SHIFT 0x05
#define AS3722_OVCURRENT_SD6_ALARM_MASK 0x07
#define AS3722_OVCURRENT_SD6_ALARM_SHIFT 0x01
#define AS3722_OVCURRENT_SD6_TRIP_MASK 0x18
#define AS3722_OVCURRENT_SD6_TRIP_SHIFT 0x03
/* AS3722 register bits and bit masks */
#define AS3722_LDO_ILIMIT_MASK BIT(7)
#define AS3722_LDO_ILIMIT_BIT BIT(7)
#define AS3722_LDO0_VSEL_MASK 0x1F
#define AS3722_LDO0_VSEL_MIN 0x01
#define AS3722_LDO0_VSEL_MAX 0x12
#define AS3722_LDO0_NUM_VOLT 0x12
#define AS3722_LDO3_VSEL_MASK 0x3F
#define AS3722_LDO3_VSEL_MIN 0x01
#define AS3722_LDO3_VSEL_MAX 0x2D
#define AS3722_LDO3_NUM_VOLT 0x2D
#define AS3722_LDO_VSEL_MASK 0x7F
#define AS3722_LDO_VSEL_MIN 0x01
#define AS3722_LDO_VSEL_MAX 0x7F
#define AS3722_LDO_VSEL_DNU_MIN 0x25
#define AS3722_LDO_VSEL_DNU_MAX 0x3F
#define AS3722_LDO_NUM_VOLT 0x80
#define AS3722_LDO0_CTRL BIT(0)
#define AS3722_LDO1_CTRL BIT(1)
#define AS3722_LDO2_CTRL BIT(2)
#define AS3722_LDO3_CTRL BIT(3)
#define AS3722_LDO4_CTRL BIT(4)
#define AS3722_LDO5_CTRL BIT(5)
#define AS3722_LDO6_CTRL BIT(6)
#define AS3722_LDO7_CTRL BIT(7)
#define AS3722_LDO9_CTRL BIT(1)
#define AS3722_LDO10_CTRL BIT(2)
#define AS3722_LDO11_CTRL BIT(3)
#define AS3722_LDO3_MODE_MASK (3 << 6)
#define AS3722_LDO3_MODE_VAL(n) (((n) & 0x3) << 6)
#define AS3722_LDO3_MODE_PMOS AS3722_LDO3_MODE_VAL(0)
#define AS3722_LDO3_MODE_PMOS_TRACKING AS3722_LDO3_MODE_VAL(1)
#define AS3722_LDO3_MODE_NMOS AS3722_LDO3_MODE_VAL(2)
#define AS3722_LDO3_MODE_SWITCH AS3722_LDO3_MODE_VAL(3)
#define AS3722_SD_VSEL_MASK 0x7F
#define AS3722_SD0_VSEL_MIN 0x01
#define AS3722_SD0_VSEL_MAX 0x5A
#define AS3722_SD2_VSEL_MIN 0x01
#define AS3722_SD2_VSEL_MAX 0x7F
#define AS3722_SDn_CTRL(n) BIT(n)
#define AS3722_SD0_MODE_FAST BIT(4)
#define AS3722_SD1_MODE_FAST BIT(4)
#define AS3722_SD2_MODE_FAST BIT(2)
#define AS3722_SD3_MODE_FAST BIT(6)
#define AS3722_SD4_MODE_FAST BIT(2)
#define AS3722_SD5_MODE_FAST BIT(2)
#define AS3722_SD6_MODE_FAST BIT(4)
#define AS3722_POWER_OFF BIT(1)
#define AS3722_INTERRUPT_MASK1_LID BIT(0)
#define AS3722_INTERRUPT_MASK1_ACOK BIT(1)
#define AS3722_INTERRUPT_MASK1_ENABLE1 BIT(2)
#define AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0 BIT(3)
#define AS3722_INTERRUPT_MASK1_ONKEY_LONG BIT(4)
#define AS3722_INTERRUPT_MASK1_ONKEY BIT(5)
#define AS3722_INTERRUPT_MASK1_OVTMP BIT(6)
#define AS3722_INTERRUPT_MASK1_LOWBAT BIT(7)
#define AS3722_INTERRUPT_MASK2_SD0_LV BIT(0)
#define AS3722_INTERRUPT_MASK2_SD1_LV BIT(1)
#define AS3722_INTERRUPT_MASK2_SD2345_LV BIT(2)
#define AS3722_INTERRUPT_MASK2_PWM1_OV_PROT BIT(3)
#define AS3722_INTERRUPT_MASK2_PWM2_OV_PROT BIT(4)
#define AS3722_INTERRUPT_MASK2_ENABLE2 BIT(5)
#define AS3722_INTERRUPT_MASK2_SD6_LV BIT(6)
#define AS3722_INTERRUPT_MASK2_RTC_REP BIT(7)
#define AS3722_INTERRUPT_MASK3_RTC_ALARM BIT(0)
#define AS3722_INTERRUPT_MASK3_GPIO1 BIT(1)
#define AS3722_INTERRUPT_MASK3_GPIO2 BIT(2)
#define AS3722_INTERRUPT_MASK3_GPIO3 BIT(3)
#define AS3722_INTERRUPT_MASK3_GPIO4 BIT(4)
#define AS3722_INTERRUPT_MASK3_GPIO5 BIT(5)
#define AS3722_INTERRUPT_MASK3_WATCHDOG BIT(6)
#define AS3722_INTERRUPT_MASK3_ENABLE3 BIT(7)
#define AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN BIT(0)
#define AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN BIT(1)
#define AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN BIT(2)
#define AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM BIT(3)
#define AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM BIT(4)
#define AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM BIT(5)
#define AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6 BIT(6)
#define AS3722_INTERRUPT_MASK4_ADC BIT(7)
#define AS3722_ADC1_INTERVAL_TIME BIT(0)
#define AS3722_ADC1_INT_MODE_ON BIT(1)
#define AS3722_ADC_BUF_ON BIT(2)
#define AS3722_ADC1_LOW_VOLTAGE_RANGE BIT(5)
#define AS3722_ADC1_INTEVAL_SCAN BIT(6)
#define AS3722_ADC1_INT_MASK BIT(7)
#define AS3722_ADC_MSB_VAL_MASK 0x7F
#define AS3722_ADC_LSB_VAL_MASK 0x07
#define AS3722_ADC0_CONV_START BIT(7)
#define AS3722_ADC0_CONV_NOTREADY BIT(7)
#define AS3722_ADC0_SOURCE_SELECT_MASK 0x1F
#define AS3722_ADC1_CONV_START BIT(7)
#define AS3722_ADC1_CONV_NOTREADY BIT(7)
#define AS3722_ADC1_SOURCE_SELECT_MASK 0x1F
/* GPIO modes */
#define AS3722_GPIO_MODE_MASK 0x07
#define AS3722_GPIO_MODE_INPUT 0x00
#define AS3722_GPIO_MODE_OUTPUT_VDDH 0x01
#define AS3722_GPIO_MODE_IO_OPEN_DRAIN 0x02
#define AS3722_GPIO_MODE_ADC_IN 0x03
#define AS3722_GPIO_MODE_INPUT_PULL_UP 0x04
#define AS3722_GPIO_MODE_INPUT_PULL_DOWN 0x05
#define AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP 0x06
#define AS3722_GPIO_MODE_OUTPUT_VDDL 0x07
#define AS3722_GPIO_MODE_VAL(n) ((n) & AS3722_GPIO_MODE_MASK)
#define AS3722_GPIO_INV BIT(7)
#define AS3722_GPIO_IOSF_MASK 0x78
#define AS3722_GPIO_IOSF_VAL(n) (((n) & 0xF) << 3)
#define AS3722_GPIO_IOSF_NORMAL AS3722_GPIO_IOSF_VAL(0)
#define AS3722_GPIO_IOSF_INTERRUPT_OUT AS3722_GPIO_IOSF_VAL(1)
#define AS3722_GPIO_IOSF_VSUP_LOW_OUT AS3722_GPIO_IOSF_VAL(2)
#define AS3722_GPIO_IOSF_GPIO_INTERRUPT_IN AS3722_GPIO_IOSF_VAL(3)
#define AS3722_GPIO_IOSF_ISINK_PWM_IN AS3722_GPIO_IOSF_VAL(4)
#define AS3722_GPIO_IOSF_VOLTAGE_STBY AS3722_GPIO_IOSF_VAL(5)
#define AS3722_GPIO_IOSF_PWR_GOOD_OUT AS3722_GPIO_IOSF_VAL(7)
#define AS3722_GPIO_IOSF_Q32K_OUT AS3722_GPIO_IOSF_VAL(8)
#define AS3722_GPIO_IOSF_WATCHDOG_IN AS3722_GPIO_IOSF_VAL(9)
#define AS3722_GPIO_IOSF_SOFT_RESET_IN AS3722_GPIO_IOSF_VAL(11)
#define AS3722_GPIO_IOSF_PWM_OUT AS3722_GPIO_IOSF_VAL(12)
#define AS3722_GPIO_IOSF_VSUP_LOW_DEB_OUT AS3722_GPIO_IOSF_VAL(13)
#define AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW AS3722_GPIO_IOSF_VAL(14)
#define AS3722_GPIOn_SIGNAL(n) BIT(n)
#define AS3722_GPIOn_CONTROL_REG(n) (AS3722_GPIO0_CONTROL_REG + n)
#define AS3722_I2C_PULL_UP BIT(4)
#define AS3722_INT_PULL_UP BIT(5)
#define AS3722_RTC_REP_WAKEUP_EN BIT(0)
#define AS3722_RTC_ALARM_WAKEUP_EN BIT(1)
#define AS3722_RTC_ON BIT(2)
#define AS3722_RTC_IRQMODE BIT(3)
#define AS3722_RTC_CLK32K_OUT_EN BIT(5)
#define AS3722_WATCHDOG_TIMER_MAX 0x7F
#define AS3722_WATCHDOG_ON BIT(0)
#define AS3722_WATCHDOG_SW_SIG BIT(0)
#define AS3722_EXT_CONTROL_ENABLE1 0x1
#define AS3722_EXT_CONTROL_ENABLE2 0x2
#define AS3722_EXT_CONTROL_ENABLE3 0x3
/* Interrupt IDs */
enum as3722_irq {
AS3722_IRQ_LID,
AS3722_IRQ_ACOK,
AS3722_IRQ_ENABLE1,
AS3722_IRQ_OCCUR_ALARM_SD0,
AS3722_IRQ_ONKEY_LONG_PRESS,
AS3722_IRQ_ONKEY,
AS3722_IRQ_OVTMP,
AS3722_IRQ_LOWBAT,
AS3722_IRQ_SD0_LV,
AS3722_IRQ_SD1_LV,
AS3722_IRQ_SD2_LV,
AS3722_IRQ_PWM1_OV_PROT,
AS3722_IRQ_PWM2_OV_PROT,
AS3722_IRQ_ENABLE2,
AS3722_IRQ_SD6_LV,
AS3722_IRQ_RTC_REP,
AS3722_IRQ_RTC_ALARM,
AS3722_IRQ_GPIO1,
AS3722_IRQ_GPIO2,
AS3722_IRQ_GPIO3,
AS3722_IRQ_GPIO4,
AS3722_IRQ_GPIO5,
AS3722_IRQ_WATCHDOG,
AS3722_IRQ_ENABLE3,
AS3722_IRQ_TEMP_SD0_SHUTDOWN,
AS3722_IRQ_TEMP_SD1_SHUTDOWN,
AS3722_IRQ_TEMP_SD2_SHUTDOWN,
AS3722_IRQ_TEMP_SD0_ALARM,
AS3722_IRQ_TEMP_SD1_ALARM,
AS3722_IRQ_TEMP_SD6_ALARM,
AS3722_IRQ_OCCUR_ALARM_SD6,
AS3722_IRQ_ADC,
AS3722_IRQ_MAX,
};
struct as3722 {
struct device *dev;
struct regmap *regmap;
int chip_irq;
unsigned long irq_flags;
bool en_intern_int_pullup;
bool en_intern_i2c_pullup;
struct regmap_irq_chip_data *irq_data;
};
static inline int as3722_read(struct as3722 *as3722, u32 reg, u32 *dest)
{
return regmap_read(as3722->regmap, reg, dest);
}
static inline int as3722_write(struct as3722 *as3722, u32 reg, u32 value)
{
return regmap_write(as3722->regmap, reg, value);
}
static inline int as3722_block_read(struct as3722 *as3722, u32 reg,
int count, u8 *buf)
{
return regmap_bulk_read(as3722->regmap, reg, buf, count);
}
static inline int as3722_block_write(struct as3722 *as3722, u32 reg,
int count, u8 *data)
{
return regmap_bulk_write(as3722->regmap, reg, data, count);
}
static inline int as3722_update_bits(struct as3722 *as3722, u32 reg,
u32 mask, u8 val)
{
return regmap_update_bits(as3722->regmap, reg, mask, val);
}
static inline int as3722_irq_get_virq(struct as3722 *as3722, int irq)
{
return regmap_irq_get_virq(as3722->irq_data, irq);
}
#endif /* __LINUX_MFD_AS3722_H__ */

8
include/linux/mfd/core.h
View File

@@ -59,6 +59,12 @@ struct mfd_cell {
* pm_runtime_no_callbacks().
*/
bool pm_runtime_no_callbacks;
/* A list of regulator supplies that should be mapped to the MFD
* device rather than the child device when requested
*/
const char **parent_supplies;
int num_parent_supplies;
};
/*
@@ -98,7 +104,7 @@ static inline const struct mfd_cell *mfd_get_cell(struct platform_device *pdev)
}
extern int mfd_add_devices(struct device *parent, int id,
struct mfd_cell *cells, int n_devs,
const struct mfd_cell *cells, int n_devs,
struct resource *mem_base,
int irq_base, struct irq_domain *irq_domain);

20
include/linux/mfd/da9052/da9052.h
View File

@@ -148,10 +148,15 @@ static inline int da9052_group_read(struct da9052 *da9052, unsigned char reg,
unsigned reg_cnt, unsigned char *val)
{
int ret;
unsigned int tmp;
int i;
ret = regmap_bulk_read(da9052->regmap, reg, val, reg_cnt);
if (ret < 0)
return ret;
for (i = 0; i < reg_cnt; i++) {
ret = regmap_read(da9052->regmap, reg + i, &tmp);
val[i] = (unsigned char)tmp;
if (ret < 0)
return ret;
}
if (da9052->fix_io) {
ret = da9052->fix_io(da9052, reg);
@@ -166,10 +171,13 @@ static inline int da9052_group_write(struct da9052 *da9052, unsigned char reg,
unsigned reg_cnt, unsigned char *val)
{
int ret;
int i;
ret = regmap_raw_write(da9052->regmap, reg, val, reg_cnt);
if (ret < 0)
return ret;
for (i = 0; i < reg_cnt; i++) {
ret = regmap_write(da9052->regmap, reg + i, val[i]);
if (ret < 0)
return ret;
}
if (da9052->fix_io) {
ret = da9052->fix_io(da9052, reg);

70
include/linux/mfd/dbx500-prcmu.h
View File

@@ -12,6 +12,8 @@
#include <linux/notifier.h>
#include <linux/err.h>
#include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */
/* Offset for the firmware version within the TCPM */
#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
@@ -94,74 +96,6 @@ enum prcmu_wakeup_index {
#define PRCMU_CLKSRC_ARMCLKFIX 0x46
#define PRCMU_CLKSRC_HDMICLK 0x47
/*
* Clock identifiers.
*/
enum prcmu_clock {
PRCMU_SGACLK,
PRCMU_UARTCLK,
PRCMU_MSP02CLK,
PRCMU_MSP1CLK,
PRCMU_I2CCLK,
PRCMU_SDMMCCLK,
PRCMU_SPARE1CLK,
PRCMU_SLIMCLK,
PRCMU_PER1CLK,
PRCMU_PER2CLK,
PRCMU_PER3CLK,
PRCMU_PER5CLK,
PRCMU_PER6CLK,
PRCMU_PER7CLK,
PRCMU_LCDCLK,
PRCMU_BMLCLK,
PRCMU_HSITXCLK,
PRCMU_HSIRXCLK,
PRCMU_HDMICLK,
PRCMU_APEATCLK,
PRCMU_APETRACECLK,
PRCMU_MCDECLK,
PRCMU_IPI2CCLK,
PRCMU_DSIALTCLK,
PRCMU_DMACLK,
PRCMU_B2R2CLK,
PRCMU_TVCLK,
PRCMU_SSPCLK,
PRCMU_RNGCLK,
PRCMU_UICCCLK,
PRCMU_PWMCLK,
PRCMU_IRDACLK,
PRCMU_IRRCCLK,
PRCMU_SIACLK,
PRCMU_SVACLK,
PRCMU_ACLK,
PRCMU_HVACLK, /* Ux540 only */
PRCMU_G1CLK, /* Ux540 only */
PRCMU_SDMMCHCLK,
PRCMU_CAMCLK,
PRCMU_BML8580CLK,
PRCMU_NUM_REG_CLOCKS,
PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
PRCMU_CDCLK,
PRCMU_TIMCLK,
PRCMU_PLLSOC0,
PRCMU_PLLSOC1,
PRCMU_ARMSS,
PRCMU_PLLDDR,
PRCMU_PLLDSI,
PRCMU_DSI0CLK,
PRCMU_DSI1CLK,
PRCMU_DSI0ESCCLK,
PRCMU_DSI1ESCCLK,
PRCMU_DSI2ESCCLK,
/* LCD DSI PLL - Ux540 only */
PRCMU_PLLDSI_LCD,
PRCMU_DSI0CLK_LCD,
PRCMU_DSI1CLK_LCD,
PRCMU_DSI0ESCCLK_LCD,
PRCMU_DSI1ESCCLK_LCD,
PRCMU_DSI2ESCCLK_LCD,
};
/**
* enum prcmu_wdog_id - PRCMU watchdog IDs
* @PRCMU_WDOG_ALL: use all timers

1
include/linux/mfd/max77693-private.h
View File

@@ -323,7 +323,6 @@ struct max77693_dev {
int irq;
int irq_gpio;
bool wakeup;
struct mutex irqlock;
int irq_masks_cur[MAX77693_IRQ_GROUP_NR];
int irq_masks_cache[MAX77693_IRQ_GROUP_NR];

2
include/linux/mfd/max77693.h
View File

@@ -64,8 +64,6 @@ struct max77693_muic_platform_data {
};
struct max77693_platform_data {
int wakeup;
/* regulator data */
struct max77693_regulator_data *regulators;
int num_regulators;

53
include/linux/mfd/rtsx_pci.h
View File

@@ -756,6 +756,59 @@
#define PCR_SETTING_REG2 0x814
#define PCR_SETTING_REG3 0x747
/* Phy bits */
#define PHY_PCR_FORCE_CODE 0xB000
#define PHY_PCR_OOBS_CALI_50 0x0800
#define PHY_PCR_OOBS_VCM_08 0x0200
#define PHY_PCR_OOBS_SEN_90 0x0040
#define PHY_PCR_RSSI_EN 0x0002
#define PHY_RCR1_ADP_TIME 0x0100
#define PHY_RCR1_VCO_COARSE 0x001F
#define PHY_RCR2_EMPHASE_EN 0x8000
#define PHY_RCR2_NADJR 0x4000
#define PHY_RCR2_CDR_CP_10 0x0400
#define PHY_RCR2_CDR_SR_2 0x0100
#define PHY_RCR2_FREQSEL_12 0x0040
#define PHY_RCR2_CPADJEN 0x0020
#define PHY_RCR2_CDR_SC_8 0x0008
#define PHY_RCR2_CALIB_LATE 0x0002
#define PHY_RDR_RXDSEL_1_9 0x4000
#define PHY_TUNE_TUNEREF_1_0 0x4000
#define PHY_TUNE_VBGSEL_1252 0x0C00
#define PHY_TUNE_SDBUS_33 0x0200
#define PHY_TUNE_TUNED18 0x01C0
#define PHY_TUNE_TUNED12 0X0020
#define PHY_BPCR_IBRXSEL 0x0400
#define PHY_BPCR_IBTXSEL 0x0100
#define PHY_BPCR_IB_FILTER 0x0080
#define PHY_BPCR_CMIRROR_EN 0x0040
#define PHY_REG_REV_RESV 0xE000
#define PHY_REG_REV_RXIDLE_LATCHED 0x1000
#define PHY_REG_REV_P1_EN 0x0800
#define PHY_REG_REV_RXIDLE_EN 0x0400
#define PHY_REG_REV_CLKREQ_DLY_TIMER_1_0 0x0040
#define PHY_REG_REV_STOP_CLKRD 0x0020
#define PHY_REG_REV_RX_PWST 0x0008
#define PHY_REG_REV_STOP_CLKWR 0x0004
#define PHY_FLD3_TIMER_4 0x7800
#define PHY_FLD3_TIMER_6 0x00E0
#define PHY_FLD3_RXDELINK 0x0004
#define PHY_FLD4_FLDEN_SEL 0x4000
#define PHY_FLD4_REQ_REF 0x2000
#define PHY_FLD4_RXAMP_OFF 0x1000
#define PHY_FLD4_REQ_ADDA 0x0800
#define PHY_FLD4_BER_COUNT 0x00E0
#define PHY_FLD4_BER_TIMER 0x000A
#define PHY_FLD4_BER_CHK_EN 0x0001
#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
struct rtsx_pcr;

1
include/linux/mfd/samsung/core.h
View File

@@ -51,6 +51,7 @@ struct sec_pmic_dev {
int ono;
int type;
bool wakeup;
bool wtsr_smpl;
};
int sec_irq_init(struct sec_pmic_dev *sec_pmic);

11
include/linux/mfd/samsung/rtc.h
View File

@@ -62,6 +62,11 @@ enum sec_rtc_reg {
/* RTC Update Register1 */
#define RTC_UDR_SHIFT 0
#define RTC_UDR_MASK (1 << RTC_UDR_SHIFT)
#define RTC_TCON_SHIFT 1
#define RTC_TCON_MASK (1 << RTC_TCON_SHIFT)
#define RTC_TIME_EN_SHIFT 3
#define RTC_TIME_EN_MASK (1 << RTC_TIME_EN_SHIFT)
/* RTC Hour register */
#define HOUR_PM_SHIFT 6
#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
@@ -69,6 +74,12 @@ enum sec_rtc_reg {
#define ALARM_ENABLE_SHIFT 7
#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
#define SMPL_ENABLE_SHIFT 7
#define SMPL_ENABLE_MASK (1 << SMPL_ENABLE_SHIFT)
#define WTSR_ENABLE_SHIFT 6
#define WTSR_ENABLE_MASK (1 << WTSR_ENABLE_SHIFT)
enum {
RTC_SEC = 0,
RTC_MIN,

2
include/linux/mfd/si476x-core.h
View File

@@ -316,7 +316,7 @@ enum si476x_smoothmetrics {
* response to 'FM_RD_STATUS' command
* @rdstpptyint: Traffic program flag(TP) and/or program type(PTY)
* code has changed.
* @rdspiint: Program indentifiaction(PI) code has changed.
* @rdspiint: Program identification(PI) code has changed.
* @rdssyncint: RDS synchronization has changed.
* @rdsfifoint: RDS was received and the RDS FIFO has at least
* 'FM_RDS_INTERRUPT_FIFO_COUNT' elements in it.

56
include/linux/mfd/stw481x.h Normal file
View File

@@ -0,0 +1,56 @@
/*
* Copyright (C) 2011 ST-Ericsson SA
* Written on behalf of Linaro for ST-Ericsson
*
* Author: Linus Walleij <linus.walleij@linaro.org>
*
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef MFD_STW481X_H
#define MFD_STW481X_H
#include <linux/i2c.h>
#include <linux/regulator/machine.h>
#include <linux/regmap.h>
#include <linux/bitops.h>
/* These registers are accessed from more than one driver */
#define STW_CONF1 0x11U
#define STW_CONF1_PDN_VMMC 0x01U
#define STW_CONF1_VMMC_MASK 0x0eU
#define STW_CONF1_VMMC_1_8V 0x02U
#define STW_CONF1_VMMC_2_85V 0x04U
#define STW_CONF1_VMMC_3V 0x06U
#define STW_CONF1_VMMC_1_85V 0x08U
#define STW_CONF1_VMMC_2_6V 0x0aU
#define STW_CONF1_VMMC_2_7V 0x0cU
#define STW_CONF1_VMMC_3_3V 0x0eU
#define STW_CONF1_MMC_LS_STATUS 0x10U
#define STW_PCTL_REG_LO 0x1eU
#define STW_PCTL_REG_HI 0x1fU
#define STW_CONF1_V_MONITORING 0x20U
#define STW_CONF1_IT_WARN 0x40U
#define STW_CONF1_PDN_VAUX 0x80U
#define STW_CONF2 0x20U
#define STW_CONF2_MASK_TWARN 0x01U
#define STW_CONF2_VMMC_EXT 0x02U
#define STW_CONF2_MASK_IT_WAKE_UP 0x04U
#define STW_CONF2_GPO1 0x08U
#define STW_CONF2_GPO2 0x10U
#define STW_VCORE_SLEEP 0x21U
/**
* struct stw481x - state holder for the Stw481x drivers
* @mutex: mutex to serialize I2C accesses
* @i2c_client: corresponding I2C client
* @regulator: regulator device for regulator children
* @map: regmap handle to access device registers
*/
struct stw481x {
struct mutex lock;
struct i2c_client *client;
struct regulator_dev *vmmc_regulator;
struct regmap *map;
};
#endif

25
include/linux/mfd/syscon.h
View File

@@ -17,10 +17,35 @@
struct device_node;
#ifdef CONFIG_MFD_SYSCON
extern struct regmap *syscon_node_to_regmap(struct device_node *np);
extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s);
extern struct regmap *syscon_regmap_lookup_by_pdevname(const char *s);
extern struct regmap *syscon_regmap_lookup_by_phandle(
struct device_node *np,
const char *property);
#else
static inline struct regmap *syscon_node_to_regmap(struct device_node *np)
{
return ERR_PTR(-ENOSYS);
}
static inline struct regmap *syscon_regmap_lookup_by_compatible(const char *s)
{
return ERR_PTR(-ENOSYS);
}
static inline struct regmap *syscon_regmap_lookup_by_pdevname(const char *s)
{
return ERR_PTR(-ENOSYS);
}
static inline struct regmap *syscon_regmap_lookup_by_phandle(
struct device_node *np,
const char *property)
{
return ERR_PTR(-ENOSYS);
}
#endif
#endif /* __LINUX_MFD_SYSCON_H__ */

13
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
View File

@@ -241,6 +241,12 @@
#define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25)
#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18)
#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12)
#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6)
#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0)
#define IMX6Q_GPR9_TZASC2_BYP BIT(1)
#define IMX6Q_GPR9_TZASC1_BYP BIT(0)
@@ -273,7 +279,9 @@
#define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
#define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25)
#define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24)
#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12)
#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4)
#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
@@ -363,4 +371,9 @@
#define IMX6Q_GPR13_SATA_TX_LVL_1_240_V (0x1f << 2)
#define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1)
#define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0)
/* For imx6sl iomux gpr register field define */
#define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
#define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */

29
include/linux/mfd/ti_am335x_tscadc.h
View File

@@ -46,16 +46,24 @@
/* Step Enable */
#define STEPENB_MASK (0x1FFFF << 0)
#define STEPENB(val) ((val) << 0)
#define ENB(val) (1 << (val))
#define STPENB_STEPENB STEPENB(0x1FFFF)
#define STPENB_STEPENB_TC STEPENB(0x1FFF)
/* IRQ enable */
#define IRQENB_HW_PEN BIT(0)
#define IRQENB_FIFO0THRES BIT(2)
#define IRQENB_FIFO0OVRRUN BIT(3)
#define IRQENB_FIFO0UNDRFLW BIT(4)
#define IRQENB_FIFO1THRES BIT(5)
#define IRQENB_FIFO1OVRRUN BIT(6)
#define IRQENB_FIFO1UNDRFLW BIT(7)
#define IRQENB_PENUP BIT(9)
/* Step Configuration */
#define STEPCONFIG_MODE_MASK (3 << 0)
#define STEPCONFIG_MODE(val) ((val) << 0)
#define STEPCONFIG_MODE_SWCNT STEPCONFIG_MODE(1)
#define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2)
#define STEPCONFIG_AVG_MASK (7 << 2)
#define STEPCONFIG_AVG(val) ((val) << 2)
@@ -123,15 +131,21 @@
#define ADC_CLK 3000000
#define TOTAL_STEPS 16
#define TOTAL_CHANNELS 8
#define FIFO1_THRESHOLD 19
/*
* ADC runs at 3MHz, and it takes
* 15 cycles to latch one data output.
* Hence the idle time for ADC to
* process one sample data would be
* around 5 micro seconds.
*/
#define IDLE_TIMEOUT 5 /* microsec */
* time in us for processing a single channel, calculated as follows:
*
* num cycles = open delay + (sample delay + conv time) * averaging
*
* num cycles: 152 + (1 + 13) * 16 = 376
*
* clock frequency: 26MHz / 8 = 3.25MHz
* clock period: 1 / 3.25MHz = 308ns
*
* processing time: 376 * 308ns = 116us
*/
#define IDLE_TIMEOUT 116 /* microsec */
#define TSCADC_CELLS 2
@@ -146,6 +160,7 @@ struct ti_tscadc_dev {
struct mfd_cell cells[TSCADC_CELLS];
u32 reg_se_cache;
spinlock_t reg_lock;
unsigned int clk_div;
/* tsc device */
struct titsc *tsc;

47
include/linux/mfd/wm8994/core.h
View File

@@ -56,8 +56,6 @@ struct irq_domain;
#define WM8994_IRQ_GPIO(x) (x + WM8994_IRQ_TEMP_WARN)
struct wm8994 {
struct mutex irq_lock;
struct wm8994_pdata pdata;
enum wm8994_type type;
@@ -85,16 +83,43 @@ struct wm8994 {
};
/* Device I/O API */
int wm8994_reg_read(struct wm8994 *wm8994, unsigned short reg);
int wm8994_reg_write(struct wm8994 *wm8994, unsigned short reg,
unsigned short val);
int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg,
unsigned short mask, unsigned short val);
int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg,
int count, u16 *buf);
int wm8994_bulk_write(struct wm8994 *wm8994, unsigned short reg,
int count, const u16 *buf);
static inline int wm8994_reg_read(struct wm8994 *wm8994, unsigned short reg)
{
unsigned int val;
int ret;
ret = regmap_read(wm8994->regmap, reg, &val);
if (ret < 0)
return ret;
else
return val;
}
static inline int wm8994_reg_write(struct wm8994 *wm8994, unsigned short reg,
unsigned short val)
{
return regmap_write(wm8994->regmap, reg, val);
}
static inline int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg,
int count, u16 *buf)
{
return regmap_bulk_read(wm8994->regmap, reg, buf, count);
}
static inline int wm8994_bulk_write(struct wm8994 *wm8994, unsigned short reg,
int count, const u16 *buf)
{
return regmap_raw_write(wm8994->regmap, reg, buf, count * sizeof(u16));
}
static inline int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg,
unsigned short mask, unsigned short val)
{
return regmap_update_bits(wm8994->regmap, reg, mask, val);
}
/* Helper to save on boilerplate */
static inline int wm8994_request_irq(struct wm8994 *wm8994, int irq,