Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc: soc specific changes (part 2) from Olof Johansson: "This adds support for the spear13xx platform, which has first been under review a long time ago and finally been completed after generic spear work has gone into the clock, dt and pinctrl branches. Also a number of updates for the samsung socs are part of this branch." Fix up trivial conflicts in drivers/gpio/gpio-samsung.c that look much worse than they are: the exonys5 init code was refactored in commitfd454997d6("gpio: samsung: refactor gpiolib init for exynos4/5"), and then commitf10590c983("ARM: EXYNOS: add GPC4 bank instance") added a new gpio chip define and did tiny updates to the init code. So the conflict diff looks like hell, but it's actually a fairly simple change. * tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (34 commits) ARM: exynos: fix building with CONFIG_OF disabled ARM: EXYNOS: Add AUXDATA for i2c controllers ARM: dts: Update device tree source files for EXYNOS5250 ARM: EXYNOS: Add device tree support for interrupt combiner ARM: EXYNOS: Add irq_domain support for interrupt combiner ARM: EXYNOS: Remove a new bus_type instance for EXYNOS5 ARM: EXYNOS: update irqs for EXYNOS5250 SoC ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll ARM: EXYNOS: add GPC4 bank instance ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition ARM: EXYNOS: Modify the GIC physical address for static io-mapping ARM: EXYNOS: Add watchdog timer clock instance pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res SPEAr: Update MAINTAINERS and Documentation SPEAr13xx: Add defconfig SPEAr13xx: Add compilation support SPEAr13xx: Add dts and dtsi files pinctrl: Add SPEAr13xx pinctrl drivers pinctrl: SPEAr: Create macro for declaring GPIO PINS SPEAr13xx: Add common clock framework support ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,52 @@
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* Samsung Exynos Interrupt Combiner Controller
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Samsung's Exynos4 architecture includes a interrupt combiner controller which
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can combine interrupt sources as a group and provide a single interrupt request
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for the group. The interrupt request from each group are connected to a parent
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interrupt controller, such as GIC in case of Exynos4210.
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The interrupt combiner controller consists of multiple combiners. Upto eight
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interrupt sources can be connected to a combiner. The combiner outputs one
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combined interrupt for its eight interrupt sources. The combined interrupt
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is usually connected to a parent interrupt controller.
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A single node in the device tree is used to describe the interrupt combiner
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controller module (which includes multiple combiners). A combiner in the
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interrupt controller module shares config/control registers with other
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combiners. For example, a 32-bit interrupt enable/disable config register
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can accommodate upto 4 interrupt combiners (with each combiner supporting
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upto 8 interrupt sources).
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Required properties:
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- compatible: should be "samsung,exynos4210-combiner".
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- interrupt-controller: Identifies the node as an interrupt controller.
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- #interrupt-cells: should be <2>. The meaning of the cells are
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* First Cell: Combiner Group Number.
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* Second Cell: Interrupt number within the group.
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- reg: Base address and size of interrupt combiner registers.
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- interrupts: The list of interrupts generated by the combiners which are then
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connected to a parent interrupt controller. The format of the interrupt
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specifier depends in the interrupt parent controller.
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Optional properties:
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- samsung,combiner-nr: The number of interrupt combiners supported. If this
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property is not specified, the default number of combiners is assumed
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to be 16.
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- interrupt-parent: pHandle of the parent interrupt controller, if not
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inherited from the parent node.
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Example:
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The following is a an example from the Exynos4210 SoC dtsi file.
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combiner:interrupt-controller@10440000 {
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compatible = "samsung,exynos4210-combiner";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x10440000 0x1000>;
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interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
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<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
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<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
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<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
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};
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@@ -2,25 +2,25 @@ ST SPEAr Platforms Device Tree Bindings
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---------------------------------------
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Boards with the ST SPEAr600 SoC shall have the following properties:
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Required root node property:
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compatible = "st,spear600";
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Boards with the ST SPEAr300 SoC shall have the following properties:
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Required root node property:
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compatible = "st,spear300";
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Boards with the ST SPEAr310 SoC shall have the following properties:
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Required root node property:
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compatible = "st,spear310";
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Boards with the ST SPEAr320 SoC shall have the following properties:
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Required root node property:
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compatible = "st,spear320";
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Boards with the ST SPEAr1310 SoC shall have the following properties:
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Required root node property:
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compatible = "st,spear1310";
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Boards with the ST SPEAr1340 SoC shall have the following properties:
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Required root node property:
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compatible = "st,spear1340";
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@@ -4,6 +4,8 @@ Required properties:
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- compatible : "st,spear300-pinmux"
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: "st,spear310-pinmux"
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: "st,spear320-pinmux"
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: "st,spear1310-pinmux"
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: "st,spear1340-pinmux"
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- reg : Address range of the pinctrl registers
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- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
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- Its values for SPEAr300:
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@@ -89,6 +91,37 @@ For SPEAr320 machines:
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"rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
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"i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
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For SPEAr1310 machines:
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"i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp",
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"i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp",
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"smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp",
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"smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp",
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"nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp",
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"keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp",
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"gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp",
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"sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp",
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"uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp",
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"uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp",
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"i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp",
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"i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp",
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"i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp",
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"can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp",
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"pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp",
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"ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp"
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For SPEAr1340 machines:
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"pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp",
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"keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp",
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"spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp",
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"pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp",
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"vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp",
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"cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp",
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"ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp",
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"uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp",
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"rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp",
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"sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp",
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"miphy_dbg_grp", "pcie_grp", "sata_grp"
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Valid values for function names are:
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For All SPEAr3xx machines:
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"firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
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@@ -106,3 +139,17 @@ For SPEAr320 machines:
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"uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
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"can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
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"mii0_1", "i2c1", "i2c2"
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For SPEAr1310 machines:
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"i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii",
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"rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0",
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"gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3",
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"uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1",
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"i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64"
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For SPEAr1340 machines:
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"pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1",
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"pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0",
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"uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf",
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"xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata"
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