MIPS: Loongson: Naming style cleanup and rework
Currently, code of Loongson-2/3 is under loongson directory and code of Loongson-1 is under loongson1 directory. Besides, there are Kconfig options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is very ugly and confusing. Since Loongson-2/3 are both 64-bit general- purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names and Kconfig symbols from loongson/loongson1 to loongson64/loongson32. [ralf@linux-mips.org: Resolve a number of simple conflicts.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/9790/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Huacai Chen
committed by
Ralf Baechle
Ralf Baechle
parent
abcc82b19f
commit
30ad29bb48
234
arch/mips/loongson32/common/platform.c
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234
arch/mips/loongson32/common/platform.c
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/*
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* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/phy.h>
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#include <linux/serial_8250.h>
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#include <linux/stmmac.h>
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#include <linux/usb/ehci_pdriver.h>
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#include <asm-generic/sizes.h>
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#include <cpufreq.h>
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#include <loongson1.h>
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/* 8250/16550 compatible UART */
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#define LS1X_UART(_id) \
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{ \
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.mapbase = LS1X_UART ## _id ## _BASE, \
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.irq = LS1X_UART ## _id ## _IRQ, \
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.iotype = UPIO_MEM, \
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.flags = UPF_IOREMAP | UPF_FIXED_TYPE, \
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.type = PORT_16550A, \
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}
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static struct plat_serial8250_port ls1x_serial8250_pdata[] = {
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LS1X_UART(0),
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LS1X_UART(1),
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LS1X_UART(2),
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LS1X_UART(3),
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{},
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};
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struct platform_device ls1x_uart_pdev = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = ls1x_serial8250_pdata,
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},
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};
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void __init ls1x_serial_setup(struct platform_device *pdev)
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{
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struct clk *clk;
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struct plat_serial8250_port *p;
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clk = clk_get(&pdev->dev, pdev->name);
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if (IS_ERR(clk)) {
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pr_err("unable to get %s clock, err=%ld",
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pdev->name, PTR_ERR(clk));
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return;
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}
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clk_prepare_enable(clk);
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for (p = pdev->dev.platform_data; p->flags != 0; ++p)
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p->uartclk = clk_get_rate(clk);
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}
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/* CPUFreq */
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static struct plat_ls1x_cpufreq ls1x_cpufreq_pdata = {
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.clk_name = "cpu_clk",
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.osc_clk_name = "osc_33m_clk",
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.max_freq = 266 * 1000,
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.min_freq = 33 * 1000,
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};
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struct platform_device ls1x_cpufreq_pdev = {
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.name = "ls1x-cpufreq",
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.dev = {
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.platform_data = &ls1x_cpufreq_pdata,
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},
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};
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/* Synopsys Ethernet GMAC */
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static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = {
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.phy_mask = 0,
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};
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static struct stmmac_dma_cfg ls1x_eth_dma_cfg = {
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.pbl = 1,
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};
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int ls1x_eth_mux_init(struct platform_device *pdev, void *priv)
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{
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struct plat_stmmacenet_data *plat_dat = NULL;
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u32 val;
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val = __raw_readl(LS1X_MUX_CTRL1);
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plat_dat = dev_get_platdata(&pdev->dev);
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if (plat_dat->bus_id) {
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__raw_writel(__raw_readl(LS1X_MUX_CTRL0) | GMAC1_USE_UART1 |
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GMAC1_USE_UART0, LS1X_MUX_CTRL0);
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switch (plat_dat->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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val &= ~(GMAC1_USE_TXCLK | GMAC1_USE_PWM23);
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break;
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case PHY_INTERFACE_MODE_MII:
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val |= (GMAC1_USE_TXCLK | GMAC1_USE_PWM23);
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break;
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default:
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pr_err("unsupported mii mode %d\n",
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plat_dat->interface);
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return -ENOTSUPP;
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}
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val &= ~GMAC1_SHUT;
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} else {
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switch (plat_dat->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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val &= ~(GMAC0_USE_TXCLK | GMAC0_USE_PWM01);
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break;
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case PHY_INTERFACE_MODE_MII:
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val |= (GMAC0_USE_TXCLK | GMAC0_USE_PWM01);
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break;
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default:
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pr_err("unsupported mii mode %d\n",
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plat_dat->interface);
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return -ENOTSUPP;
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}
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val &= ~GMAC0_SHUT;
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}
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__raw_writel(val, LS1X_MUX_CTRL1);
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return 0;
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}
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static struct plat_stmmacenet_data ls1x_eth0_pdata = {
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.bus_id = 0,
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.phy_addr = -1,
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.interface = PHY_INTERFACE_MODE_MII,
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.mdio_bus_data = &ls1x_mdio_bus_data,
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.dma_cfg = &ls1x_eth_dma_cfg,
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.has_gmac = 1,
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.tx_coe = 1,
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.init = ls1x_eth_mux_init,
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};
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static struct resource ls1x_eth0_resources[] = {
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[0] = {
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.start = LS1X_GMAC0_BASE,
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.end = LS1X_GMAC0_BASE + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.name = "macirq",
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.start = LS1X_GMAC0_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device ls1x_eth0_pdev = {
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.name = "stmmaceth",
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.id = 0,
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.num_resources = ARRAY_SIZE(ls1x_eth0_resources),
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.resource = ls1x_eth0_resources,
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.dev = {
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.platform_data = &ls1x_eth0_pdata,
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},
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};
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static struct plat_stmmacenet_data ls1x_eth1_pdata = {
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.bus_id = 1,
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.phy_addr = -1,
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.interface = PHY_INTERFACE_MODE_MII,
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.mdio_bus_data = &ls1x_mdio_bus_data,
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.dma_cfg = &ls1x_eth_dma_cfg,
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.has_gmac = 1,
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.tx_coe = 1,
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.init = ls1x_eth_mux_init,
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};
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static struct resource ls1x_eth1_resources[] = {
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[0] = {
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.start = LS1X_GMAC1_BASE,
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.end = LS1X_GMAC1_BASE + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.name = "macirq",
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.start = LS1X_GMAC1_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device ls1x_eth1_pdev = {
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.name = "stmmaceth",
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.id = 1,
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.num_resources = ARRAY_SIZE(ls1x_eth1_resources),
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.resource = ls1x_eth1_resources,
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.dev = {
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.platform_data = &ls1x_eth1_pdata,
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},
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};
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/* USB EHCI */
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static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32);
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static struct resource ls1x_ehci_resources[] = {
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[0] = {
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.start = LS1X_EHCI_BASE,
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.end = LS1X_EHCI_BASE + SZ_32K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = LS1X_EHCI_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct usb_ehci_pdata ls1x_ehci_pdata = {
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};
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struct platform_device ls1x_ehci_pdev = {
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.name = "ehci-platform",
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.id = -1,
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.num_resources = ARRAY_SIZE(ls1x_ehci_resources),
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.resource = ls1x_ehci_resources,
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.dev = {
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.dma_mask = &ls1x_ehci_dmamask,
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.platform_data = &ls1x_ehci_pdata,
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},
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};
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/* Real Time Clock */
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struct platform_device ls1x_rtc_pdev = {
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.name = "ls1x-rtc",
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.id = -1,
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};
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