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ARM: tegra: Move includes to include/soc/tegra

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In order to not clutter the include/linux directory with SoC specific
headers, move the Tegra-specific headers out into a separate directory.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
2014-07-17 13:17:24 +02:00
parent 7171511eae
commit 306a7f9139
15 changed files with 37 additions and 24 deletions
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19
include/soc/tegra/ahb.h Normal file
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@@ -0,0 +1,19 @@
/*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __SOC_TEGRA_AHB_H__
#define __SOC_TEGRA_AHB_H__
extern int tegra_ahb_enable_smmu(struct device_node *ahb);
#endif /* __SOC_TEGRA_AHB_H__ */

25
include/soc/tegra/cpuidle.h Normal file
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@@ -0,0 +1,25 @@
/*
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __SOC_TEGRA_CPUIDLE_H__
#define __SOC_TEGRA_CPUIDLE_H__
#ifdef CONFIG_CPU_IDLE
void tegra_cpuidle_pcie_irqs_in_use(void);
#else
static inline void tegra_cpuidle_pcie_irqs_in_use(void)
{
}
#endif
#endif /* __SOC_TEGRA_CPUIDLE_H__ */

22
include/soc/tegra/fuse.h Normal file
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@@ -0,0 +1,22 @@
/*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __SOC_TEGRA_FUSE_H__
#define __SOC_TEGRA_FUSE_H__
u32 tegra_read_chipid(void);
#endif /* __SOC_TEGRA_FUSE_H__ */

134
include/soc/tegra/powergate.h Normal file
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/*
* Copyright (c) 2010 Google, Inc
*
* Author:
* Colin Cross <ccross@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __SOC_TEGRA_POWERGATE_H__
#define __SOC_TEGRA_POWERGATE_H__
struct clk;
struct reset_control;
#define TEGRA_POWERGATE_CPU 0
#define TEGRA_POWERGATE_3D 1
#define TEGRA_POWERGATE_VENC 2
#define TEGRA_POWERGATE_PCIE 3
#define TEGRA_POWERGATE_VDEC 4
#define TEGRA_POWERGATE_L2 5
#define TEGRA_POWERGATE_MPE 6
#define TEGRA_POWERGATE_HEG 7
#define TEGRA_POWERGATE_SATA 8
#define TEGRA_POWERGATE_CPU1 9
#define TEGRA_POWERGATE_CPU2 10
#define TEGRA_POWERGATE_CPU3 11
#define TEGRA_POWERGATE_CELP 12
#define TEGRA_POWERGATE_3D1 13
#define TEGRA_POWERGATE_CPU0 14
#define TEGRA_POWERGATE_C0NC 15
#define TEGRA_POWERGATE_C1NC 16
#define TEGRA_POWERGATE_SOR 17
#define TEGRA_POWERGATE_DIS 18
#define TEGRA_POWERGATE_DISB 19
#define TEGRA_POWERGATE_XUSBA 20
#define TEGRA_POWERGATE_XUSBB 21
#define TEGRA_POWERGATE_XUSBC 22
#define TEGRA_POWERGATE_VIC 23
#define TEGRA_POWERGATE_IRAM 24
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
#define TEGRA_IO_RAIL_CSIA 0
#define TEGRA_IO_RAIL_CSIB 1
#define TEGRA_IO_RAIL_DSI 2
#define TEGRA_IO_RAIL_MIPI_BIAS 3
#define TEGRA_IO_RAIL_PEX_BIAS 4
#define TEGRA_IO_RAIL_PEX_CLK1 5
#define TEGRA_IO_RAIL_PEX_CLK2 6
#define TEGRA_IO_RAIL_USB0 9
#define TEGRA_IO_RAIL_USB1 10
#define TEGRA_IO_RAIL_USB2 11
#define TEGRA_IO_RAIL_USB_BIAS 12
#define TEGRA_IO_RAIL_NAND 13
#define TEGRA_IO_RAIL_UART 14
#define TEGRA_IO_RAIL_BB 15
#define TEGRA_IO_RAIL_AUDIO 17
#define TEGRA_IO_RAIL_HSIC 19
#define TEGRA_IO_RAIL_COMP 22
#define TEGRA_IO_RAIL_HDMI 28
#define TEGRA_IO_RAIL_PEX_CNTRL 32
#define TEGRA_IO_RAIL_SDMMC1 33
#define TEGRA_IO_RAIL_SDMMC3 34
#define TEGRA_IO_RAIL_SDMMC4 35
#define TEGRA_IO_RAIL_CAM 36
#define TEGRA_IO_RAIL_RES 37
#define TEGRA_IO_RAIL_HV 38
#define TEGRA_IO_RAIL_DSIB 39
#define TEGRA_IO_RAIL_DSIC 40
#define TEGRA_IO_RAIL_DSID 41
#define TEGRA_IO_RAIL_CSIE 44
#define TEGRA_IO_RAIL_LVDS 57
#define TEGRA_IO_RAIL_SYS_DDC 58
#ifdef CONFIG_ARCH_TEGRA
int tegra_powergate_is_powered(int id);
int tegra_powergate_power_on(int id);
int tegra_powergate_power_off(int id);
int tegra_powergate_remove_clamping(int id);
/* Must be called with clk disabled, and returns with clk enabled */
int tegra_powergate_sequence_power_up(int id, struct clk *clk,
struct reset_control *rst);
int tegra_io_rail_power_on(int id);
int tegra_io_rail_power_off(int id);
#else
static inline int tegra_powergate_is_powered(int id)
{
return -ENOSYS;
}
static inline int tegra_powergate_power_on(int id)
{
return -ENOSYS;
}
static inline int tegra_powergate_power_off(int id)
{
return -ENOSYS;
}
static inline int tegra_powergate_remove_clamping(int id)
{
return -ENOSYS;
}
static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk,
struct reset_control *rst)
{
return -ENOSYS;
}
static inline int tegra_io_rail_power_on(int id)
{
return -ENOSYS;
}
static inline int tegra_io_rail_power_off(int id)
{
return -ENOSYS;
}
#endif
#endif /* __SOC_TEGRA_POWERGATE_H__ */