Merge tag 'media/v4.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media

Pull media updates from Mauro Carvalho Chehab:

 - remove of atomisp driver from staging, as nobody would have time to
   dedicate huge efforts to fix all the problems there. Also, we have a
   feeling that the driver may not even run the way it is.

 - move Zoran driver to staging, in order to be either fixed to use VB2
   and the proper media kAPIs or to be removed

 - remove videobuf-dvb driver, with is unused for a while

 - some V4L2 documentation fixes/improvements

 - new sensor drivers: imx258 and ov7251

 - a new driver was added to allow using I2C transparent drivers

 - several improvements at the ddbridge driver

 - several improvements at the ISDB pt1 driver, making it more coherent
   with the DVB framework

 - added a new platform driver for MIPI CSI-2 RX: cadence

 - now, all media drivers can be compiled on x86 with COMPILE_TEST

 - almost all media drivers now build on non-x86 architectures with
   COMPILE_TEST

 - lots of other random stuff: cleanups, support for new board models,
   bug fixes, etc

* tag 'media/v4.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (464 commits)
  media: omap2: fix compile-testing with FB_OMAP2=m
  media: media/radio/Kconfig: add back RADIO_ISA
  media: v4l2-ioctl.c: fix missing unlock in __video_do_ioctl()
  media: pxa_camera: ignore -ENOIOCTLCMD from v4l2_subdev_call for s_power
  media: arch: sh: migor: Fix TW9910 PDN gpio
  media: staging: tegra-vde: Reset VDE regardless of memory client resetting failure
  media: marvel-ccic: mmp: select VIDEOBUF2_VMALLOC/DMA_CONTIG
  media: marvel-ccic: allow ccic and mmp drivers to coexist
  media: uvcvideo: Prevent setting unavailable flags
  media: ddbridge: conditionally enable fast TS for stv0910-equipped bridges
  media: dvb-frontends/stv0910: make TS speed configurable
  media: ddbridge/mci: add identifiers to function definition arguments
  media: ddbridge/mci: protect against out-of-bounds array access in stop()
  media: rc: ensure input/lirc device can be opened after register
  media: rc: nuvoton: Keep device enabled during reg init
  media: rc: nuvoton: Keep track of users on CIR enable/disable
  media: rc: nuvoton: Tweak the interrupt enabling dance
  media: uvcvideo: Support realtek's UVC 1.5 device
  media: uvcvideo: Fix driver reference counting
  media: gspca_zc3xx: Enable short exposure times for OV7648
  ...
This commit is contained in:
Linus Torvalds
2018-06-07 12:34:37 -07:00
1168 changed files with 16826 additions and 176711 deletions

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@@ -0,0 +1,100 @@
Cadence MIPI-CSI2 RX controller
===============================
The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
lanes in input, and 4 different pixel streams in output.
Required properties:
- compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
- reg: base address and size of the memory mapped region
- clocks: phandles to the clocks driving the controller
- clock-names: must contain:
* sys_clk: main clock
* p_clk: register bank clock
* pixel_if[0-3]_clk: pixel stream output clock, one for each stream
implemented in hardware, between 0 and 3
Optional properties:
- phys: phandle to the external D-PHY, phy-names must be provided
- phy-names: must contain "dphy", if the implementation uses an
external D-PHY
Required subnodes:
- ports: A ports node with one port child node per device input and output
port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
port nodes are numbered as follows:
Port Description
-----------------------------
0 CSI-2 input
1 Stream 0 output
2 Stream 1 output
3 Stream 2 output
4 Stream 3 output
The stream output port nodes are optional if they are not
connected to anything at the hardware level or implemented
in the design.Since there is only one endpoint per port,
the endpoints are not numbered.
Example:
csi2rx: csi-bridge@0d060000 {
compatible = "cdns,csi2rx";
reg = <0x0d060000 0x1000>;
clocks = <&byteclock>, <&byteclock>
<&coreclock>, <&coreclock>,
<&coreclock>, <&coreclock>;
clock-names = "sys_clk", "p_clk",
"pixel_if0_clk", "pixel_if1_clk",
"pixel_if2_clk", "pixel_if3_clk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi2rx_in_sensor: endpoint {
remote-endpoint = <&sensor_out_csi2rx>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
csi2rx_out_grabber0: endpoint {
remote-endpoint = <&grabber0_in_csi2rx>;
};
};
port@2 {
reg = <2>;
csi2rx_out_grabber1: endpoint {
remote-endpoint = <&grabber1_in_csi2rx>;
};
};
port@3 {
reg = <3>;
csi2rx_out_grabber2: endpoint {
remote-endpoint = <&grabber2_in_csi2rx>;
};
};
port@4 {
reg = <4>;
csi2rx_out_grabber3: endpoint {
remote-endpoint = <&grabber3_in_csi2rx>;
};
};
};
};

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@@ -0,0 +1,98 @@
Cadence MIPI-CSI2 TX controller
===============================
The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
4 CSI lanes in output, and up to 4 different pixel streams in input.
Required properties:
- compatible: must be set to "cdns,csi2tx"
- reg: base address and size of the memory mapped region
- clocks: phandles to the clocks driving the controller
- clock-names: must contain:
* esc_clk: escape mode clock
* p_clk: register bank clock
* pixel_if[0-3]_clk: pixel stream output clock, one for each stream
implemented in hardware, between 0 and 3
Optional properties
- phys: phandle to the D-PHY. If it is set, phy-names need to be set
- phy-names: must contain "dphy"
Required subnodes:
- ports: A ports node with one port child node per device input and output
port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
port nodes are numbered as follows.
Port Description
-----------------------------
0 CSI-2 output
1 Stream 0 input
2 Stream 1 input
3 Stream 2 input
4 Stream 3 input
The stream input port nodes are optional if they are not
connected to anything at the hardware level or implemented
in the design. Since there is only one endpoint per port,
the endpoints are not numbered.
Example:
csi2tx: csi-bridge@0d0e1000 {
compatible = "cdns,csi2tx";
reg = <0x0d0e1000 0x1000>;
clocks = <&byteclock>, <&byteclock>,
<&coreclock>, <&coreclock>,
<&coreclock>, <&coreclock>;
clock-names = "p_clk", "esc_clk",
"pixel_if0_clk", "pixel_if1_clk",
"pixel_if2_clk", "pixel_if3_clk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi2tx_out: endpoint {
remote-endpoint = <&remote_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
csi2tx_in_stream0: endpoint {
remote-endpoint = <&stream0_out>;
};
};
port@2 {
reg = <2>;
csi2tx_in_stream1: endpoint {
remote-endpoint = <&stream1_out>;
};
};
port@3 {
reg = <3>;
csi2tx_in_stream2: endpoint {
remote-endpoint = <&stream2_out>;
};
};
port@4 {
reg = <4>;
csi2tx_in_stream3: endpoint {
remote-endpoint = <&stream3_out>;
};
};
};
};

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@@ -0,0 +1,52 @@
* Omnivision 1/7.5-Inch B&W VGA CMOS Digital Image Sensor
The Omnivision OV7251 is a 1/7.5-Inch CMOS active pixel digital image sensor
with an active array size of 640H x 480V. It is programmable through a serial
I2C interface.
Required Properties:
- compatible: Value should be "ovti,ov7251".
- clocks: Reference to the xclk clock.
- clock-names: Should be "xclk".
- clock-frequency: Frequency of the xclk clock.
- enable-gpios: Chip enable GPIO. Polarity is GPIO_ACTIVE_HIGH. This corresponds
to the hardware pin XSHUTDOWN which is physically active low.
- vdddo-supply: Chip digital IO regulator.
- vdda-supply: Chip analog regulator.
- vddd-supply: Chip digital core regulator.
The device node shall contain one 'port' child node with a single 'endpoint'
subnode for its digital output video port, in accordance with the video
interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
&i2c1 {
...
ov7251: camera-sensor@60 {
compatible = "ovti,ov7251";
reg = <0x60>;
enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&camera_bw_default>;
clocks = <&clks 200>;
clock-names = "xclk";
clock-frequency = <24000000>;
vdddo-supply = <&camera_dovdd_1v8>;
vdda-supply = <&camera_avdd_2v8>;
vddd-supply = <&camera_dvdd_1v2>;
port {
ov7251_ep: endpoint {
clock-lanes = <1>;
data-lanes = <0>;
remote-endpoint = <&csi0_ep>;
};
};
};
};

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@@ -0,0 +1,40 @@
* Omnivision OV7720/OV7725 CMOS sensor
The Omnivision OV7720/OV7725 sensor supports multiple resolutions output,
such as VGA, QVGA, and any size scaling down from CIF to 40x30. It also can
support the YUV422, RGB565/555/444, GRB422 or raw RGB output formats.
Required Properties:
- compatible: shall be one of
"ovti,ov7720"
"ovti,ov7725"
- clocks: reference to the xclk input clock.
Optional Properties:
- reset-gpios: reference to the GPIO connected to the RSTB pin which is
active low, if any.
- powerdown-gpios: reference to the GPIO connected to the PWDN pin which is
active high, if any.
The device node shall contain one 'port' child node with one child 'endpoint'
subnode for its digital output video port, in accordance with the video
interface bindings defined in Documentation/devicetree/bindings/media/
video-interfaces.txt.
Example:
&i2c0 {
ov772x: camera@21 {
compatible = "ovti,ov7725";
reg = <0x21>;
reset-gpios = <&axi_gpio_0 0 GPIO_ACTIVE_LOW>;
powerdown-gpios = <&axi_gpio_0 1 GPIO_ACTIVE_LOW>;
clocks = <&xclk>;
port {
ov772x_0: endpoint {
remote-endpoint = <&vcap1_in0>;
};
};
};
};

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@@ -0,0 +1,19 @@
* Panasonic AMG88xx
The Panasonic family of AMG88xx Grid-Eye sensors allow recording
8x8 10Hz video which consists of thermal datapoints
Required Properties:
- compatible : Must be "panasonic,amg88xx"
- reg : i2c address of the device
Example:
i2c0@1c22000 {
...
amg88xx@69 {
compatible = "panasonic,amg88xx";
reg = <0x69>;
};
...
};

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@@ -2,20 +2,28 @@ Renesas R-Car Video Input driver (rcar_vin)
-------------------------------------------
The rcar_vin device provides video input capabilities for the Renesas R-Car
family of devices. The current blocks are always slaves and suppot one input
channel which can be either RGB, YUYV or BT656.
family of devices.
Each VIN instance has a single parallel input that supports RGB and YUV video,
with both external synchronization and BT.656 synchronization for the latter.
Depending on the instance the VIN input is connected to external SoC pins, or
on Gen3 platforms to a CSI-2 receiver.
- compatible: Must be one or more of the following
- "renesas,vin-r8a7795" for the R8A7795 device
- "renesas,vin-r8a7794" for the R8A7794 device
- "renesas,vin-r8a7793" for the R8A7793 device
- "renesas,vin-r8a7792" for the R8A7792 device
- "renesas,vin-r8a7791" for the R8A7791 device
- "renesas,vin-r8a7790" for the R8A7790 device
- "renesas,vin-r8a7779" for the R8A7779 device
- "renesas,vin-r8a7743" for the R8A7743 device
- "renesas,vin-r8a7745" for the R8A7745 device
- "renesas,vin-r8a7778" for the R8A7778 device
- "renesas,rcar-gen2-vin" for a generic R-Car Gen2 compatible device.
- "renesas,rcar-gen3-vin" for a generic R-Car Gen3 compatible device.
- "renesas,vin-r8a7779" for the R8A7779 device
- "renesas,vin-r8a7790" for the R8A7790 device
- "renesas,vin-r8a7791" for the R8A7791 device
- "renesas,vin-r8a7792" for the R8A7792 device
- "renesas,vin-r8a7793" for the R8A7793 device
- "renesas,vin-r8a7794" for the R8A7794 device
- "renesas,vin-r8a7795" for the R8A7795 device
- "renesas,vin-r8a7796" for the R8A7796 device
- "renesas,vin-r8a77970" for the R8A77970 device
- "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible
device.
When compatible with the generic version nodes must list the
SoC-specific version corresponding to the platform first
@@ -28,21 +36,38 @@ channel which can be either RGB, YUYV or BT656.
Additionally, an alias named vinX will need to be created to specify
which video input device this is.
The per-board settings:
The per-board settings Gen2 platforms:
- port sub-node describing a single endpoint connected to the vin
as described in video-interfaces.txt[1]. Only the first one will
be considered as each vin interface has one input port.
These settings are used to work out video input format and widths
into the system.
The per-board settings Gen3 platforms:
Gen3 platforms can support both a single connected parallel input source
from external SoC pins (port0) and/or multiple parallel input sources
from local SoC CSI-2 receivers (port1) depending on SoC.
Device node example
-------------------
- renesas,id - ID number of the VIN, VINx in the documentation.
- ports
- port 0 - sub-node describing a single endpoint connected to the VIN
from external SoC pins described in video-interfaces.txt[1].
Describing more then one endpoint in port 0 is invalid. Only VIN
instances that are connected to external pins should have port 0.
- port 1 - sub-nodes describing one or more endpoints connected to
the VIN from local SoC CSI-2 receivers. The endpoint numbers must
use the following schema.
aliases {
vin0 = &vin0;
};
- Endpoint 0 - sub-node describing the endpoint connected to CSI20
- Endpoint 1 - sub-node describing the endpoint connected to CSI21
- Endpoint 2 - sub-node describing the endpoint connected to CSI40
- Endpoint 3 - sub-node describing the endpoint connected to CSI41
Device node example for Gen2 platforms
--------------------------------------
aliases {
vin0 = &vin0;
};
vin0: vin@e6ef0000 {
compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
@@ -52,8 +77,8 @@ Device node example
status = "disabled";
};
Board setup example (vin1 composite video input)
------------------------------------------------
Board setup example for Gen2 platforms (vin1 composite video input)
-------------------------------------------------------------------
&i2c2 {
status = "okay";
@@ -92,6 +117,77 @@ Board setup example (vin1 composite video input)
};
};
Device node example for Gen3 platforms
--------------------------------------
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a7795";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 811>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 811>;
renesas,id = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin0csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin0>;
};
vin0csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin0>;
};
vin0csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin0>;
};
};
};
};
csi20: csi2@fea80000 {
compatible = "renesas,r8a7795-csi2";
reg = <0 0xfea80000 0 0x10000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 714>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 714>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi20_in: endpoint {
clock-lanes = <0>;
data-lanes = <1>;
remote-endpoint = <&adv7482_txb>;
};
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi20vin0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin0csi20>;
};
};
};
};
[1] video-interfaces.txt common video media interface

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@@ -2,14 +2,15 @@ Renesas Capture Engine Unit (CEU)
----------------------------------------------
The Capture Engine Unit is the image capture interface found in the Renesas
SH Mobile and RZ SoCs.
SH Mobile, R-Mobile and RZ SoCs.
The interface supports a single parallel input with data bus width of 8 or 16
bits.
Required properties:
- compatible: Shall be "renesas,r7s72100-ceu" for CEU units found in RZ/A1H
and RZ/A1M SoCs.
- compatible: Shall be one of the following values:
"renesas,r7s72100-ceu" for CEU units found in RZ/A1H and RZ/A1M SoCs
"renesas,r8a7740-ceu" for CEU units found in R-Mobile A1 R8A7740 SoCs
- reg: Registers address base and size.
- interrupts: The interrupt specifier.

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@@ -0,0 +1,101 @@
Renesas R-Car MIPI CSI-2
------------------------
The R-Car CSI-2 receiver device provides MIPI CSI-2 capabilities for the
Renesas R-Car family of devices. It is used in conjunction with the
R-Car VIN module, which provides the video capture capabilities.
Mandatory properties
--------------------
- compatible: Must be one or more of the following
- "renesas,r8a7795-csi2" for the R8A7795 device.
- "renesas,r8a7796-csi2" for the R8A7796 device.
- "renesas,r8a77965-csi2" for the R8A77965 device.
- "renesas,r8a77970-csi2" for the R8A77970 device.
- reg: the register base and size for the device registers
- interrupts: the interrupt for the device
- clocks: reference to the parent clock
The device node shall contain two 'port' child nodes according to the
bindings defined in Documentation/devicetree/bindings/media/
video-interfaces.txt. port@0 shall connect to the CSI-2 source. port@1
shall connect to all the R-Car VIN modules that have a hardware
connection to the CSI-2 receiver.
- port@0- Video source (mandatory)
- endpoint@0 - sub-node describing the endpoint that is the video source
- port@1 - VIN instances (optional)
- One endpoint sub-node for every R-Car VIN instance which is connected
to the R-Car CSI-2 receiver.
Example:
csi20: csi2@fea80000 {
compatible = "renesas,r8a7796-csi2";
reg = <0 0xfea80000 0 0x10000>;
interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 714>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 714>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
csi20_in: endpoint@0 {
reg = <0>;
clock-lanes = <0>;
data-lanes = <1>;
remote-endpoint = <&adv7482_txb>;
};
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi20vin0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin0csi20>;
};
csi20vin1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin1csi20>;
};
csi20vin2: endpoint@2 {
reg = <2>;
remote-endpoint = <&vin2csi20>;
};
csi20vin3: endpoint@3 {
reg = <3>;
remote-endpoint = <&vin3csi20>;
};
csi20vin4: endpoint@4 {
reg = <4>;
remote-endpoint = <&vin4csi20>;
};
csi20vin5: endpoint@5 {
reg = <5>;
remote-endpoint = <&vin5csi20>;
};
csi20vin6: endpoint@6 {
reg = <6>;
remote-endpoint = <&vin6csi20>;
};
csi20vin7: endpoint@7 {
reg = <7>;
remote-endpoint = <&vin7csi20>;
};
};
};
};