Merge tag 'mfd_3.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
Pull MFD changes from Samuel Ortiz: - 4 new drivers: Freescale i.MX on-chip Anatop, Ricoh's RC5T583 and TI's TPS65090 and TPS65217. - New variants support (8420, 8520 ab9540), cleanups and bug fixes for the abx500 and db8500 ST-E chipsets. - Some minor fixes and update for the wm8994 from Mark. - The beginning of a long term TWL cleanup effort coming from the TI folks. - Various fixes and cleanups for the s5m, TPS659xx, pm860x, and MAX8997 drivers. Fix up trivial conflicts due to duplicate patches and header file cleanups (<linux/device.h> removal etc). * tag 'mfd_3.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (97 commits) gpio/twl: Add DT support to gpio-twl4030 driver gpio/twl: Allocate irq_desc dynamically for SPARSE_IRQ support mfd: Detach twl6040 from the pmic mfd driver mfd: Replace twl-* pr_ macros by the dev_ equivalent and do various cleanups mfd: Micro-optimization on twl4030 IRQ handler mfd: Make twl4030 SIH SPARSE_IRQ capable mfd: Move twl-core IRQ allocation into twl[4030|6030]-irq files mfd: Remove references already defineid in header file from twl-core mfd: Remove unneeded header from twl-core mfd: Make twl-core not depend on pdata->irq_base/end ARM: OMAP2+: board-omap4-*: Do not use anymore TWL6030_IRQ_BASE in board files mfd: Return twl6030_mmc_card_detect IRQ for board setup Revert "mfd: Add platform data for MAX8997 haptic driver" mfd: Add support for TPS65090 mfd: Add some da9052-i2c section annotations mfd: Build rtc5t583 only if I2C config is selected to y. mfd: Add anatop mfd driver mfd: Fix compilation error in tps65910.h mfd: Add 8420 variant to db8500-prcmu mfd: Add 8520 PRCMU variant to db8500-prcmu ...
This commit is contained in:
Linus Torvalds
@@ -10,12 +10,14 @@
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/*
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* Platform data to register a block: only the initial gpio/irq number.
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* Array sizes are large enough to contain all AB8500 and AB9540 GPIO
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* registers.
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*/
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struct ab8500_gpio_platform_data {
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int gpio_base;
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u32 irq_base;
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u8 config_reg[7];
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u8 config_reg[8];
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};
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#endif /* _AB8500_GPIO_H */
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@@ -71,6 +71,13 @@ static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
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#define AB8500_SWATCTRL 0x230
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#define AB8500_HIQCLKCTRL 0x232
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#define AB8500_VSIMSYSCLKCTRL 0x233
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#define AB9540_SYSCLK12BUFCTRL 0x234
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#define AB9540_SYSCLK12CONFCTRL 0x235
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#define AB9540_SYSCLK12BUFCTRL2 0x236
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#define AB9540_SYSCLK12BUF1VALID 0x237
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#define AB9540_SYSCLK12BUF2VALID 0x238
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#define AB9540_SYSCLK12BUF3VALID 0x239
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#define AB9540_SYSCLK12BUF4VALID 0x23A
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/* Bits */
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#define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
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@@ -251,4 +258,40 @@ static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
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#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
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#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
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#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0)
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#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1)
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#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2)
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#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3)
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#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK 0x0F
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#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4)
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#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5)
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#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6)
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#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7)
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#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK 0xF0
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#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
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#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
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#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C
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#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2
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#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
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#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
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#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
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#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0)
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#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1)
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#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2)
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#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3)
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#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK 0xFF
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#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT 0
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#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK 0xFF
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#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT 0
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#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK 0xFF
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#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT 0
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#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF
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#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0
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#endif /* __AB8500_SYSCTRL_H */
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@@ -11,6 +11,29 @@
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struct device;
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/*
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* AB IC versions
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*
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* AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a
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* non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the
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* print of version string.
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*/
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enum ab8500_version {
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AB8500_VERSION_AB8500 = 0x0,
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AB8500_VERSION_AB8505 = 0x1,
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AB8500_VERSION_AB9540 = 0x2,
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AB8500_VERSION_AB8540 = 0x3,
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AB8500_VERSION_UNDEFINED,
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};
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/* AB8500 CIDs*/
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#define AB8500_CUTEARLY 0x00
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#define AB8500_CUT1P0 0x10
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#define AB8500_CUT1P1 0x11
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#define AB8500_CUT2P0 0x20
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#define AB8500_CUT3P0 0x30
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#define AB8500_CUT3P3 0x33
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/*
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* AB8500 bank addresses
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*/
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@@ -37,30 +60,34 @@ struct device;
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/*
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* Interrupts
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* Values used to index into array ab8500_irq_regoffset[] defined in
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* drivers/mdf/ab8500-core.c
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*/
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#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0
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#define AB8500_INT_UN_PLUG_TV_DET 1
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#define AB8500_INT_PLUG_TV_DET 2
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/* Definitions for AB8500 and AB9540 */
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/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
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#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */
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#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540 */
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#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540 */
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#define AB8500_INT_TEMP_WARM 3
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#define AB8500_INT_PON_KEY2DB_F 4
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#define AB8500_INT_PON_KEY2DB_R 5
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#define AB8500_INT_PON_KEY1DB_F 6
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#define AB8500_INT_PON_KEY1DB_R 7
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/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
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#define AB8500_INT_BATT_OVV 8
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#define AB8500_INT_MAIN_CH_UNPLUG_DET 10
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#define AB8500_INT_MAIN_CH_PLUG_DET 11
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#define AB8500_INT_USB_ID_DET_F 12
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#define AB8500_INT_USB_ID_DET_R 13
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#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505 */
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#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505 */
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#define AB8500_INT_VBUS_DET_F 14
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#define AB8500_INT_VBUS_DET_R 15
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/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
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#define AB8500_INT_VBUS_CH_DROP_END 16
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#define AB8500_INT_RTC_60S 17
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#define AB8500_INT_RTC_ALARM 18
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#define AB8500_INT_BAT_CTRL_INDB 20
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#define AB8500_INT_CH_WD_EXP 21
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#define AB8500_INT_VBUS_OVV 22
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#define AB8500_INT_MAIN_CH_DROP_END 23
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#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540 */
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/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
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#define AB8500_INT_CCN_CONV_ACC 24
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#define AB8500_INT_INT_AUD 25
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#define AB8500_INT_CCEOC 26
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@@ -69,7 +96,8 @@ struct device;
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#define AB8500_INT_LOW_BAT_R 29
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#define AB8500_INT_BUP_CHG_NOT_OK 30
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#define AB8500_INT_BUP_CHG_OK 31
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#define AB8500_INT_GP_HW_ADC_CONV_END 32
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/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
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#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505 */
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#define AB8500_INT_ACC_DETECT_1DB_F 33
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#define AB8500_INT_ACC_DETECT_1DB_R 34
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#define AB8500_INT_ACC_DETECT_22DB_F 35
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@@ -77,38 +105,43 @@ struct device;
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#define AB8500_INT_ACC_DETECT_21DB_F 37
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#define AB8500_INT_ACC_DETECT_21DB_R 38
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#define AB8500_INT_GP_SW_ADC_CONV_END 39
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#define AB8500_INT_GPIO6R 40
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#define AB8500_INT_GPIO7R 41
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#define AB8500_INT_GPIO8R 42
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#define AB8500_INT_GPIO9R 43
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/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
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#define AB8500_INT_GPIO6R 40 /* not 8505/9540 */
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#define AB8500_INT_GPIO7R 41 /* not 8505/9540 */
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#define AB8500_INT_GPIO8R 42 /* not 8505/9540 */
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#define AB8500_INT_GPIO9R 43 /* not 8505/9540 */
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#define AB8500_INT_GPIO10R 44
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#define AB8500_INT_GPIO11R 45
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#define AB8500_INT_GPIO12R 46
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#define AB8500_INT_GPIO12R 46 /* not 8505 */
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#define AB8500_INT_GPIO13R 47
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#define AB8500_INT_GPIO24R 48
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#define AB8500_INT_GPIO25R 49
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#define AB8500_INT_GPIO36R 50
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#define AB8500_INT_GPIO37R 51
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#define AB8500_INT_GPIO38R 52
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#define AB8500_INT_GPIO39R 53
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/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
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#define AB8500_INT_GPIO24R 48 /* not 8505 */
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#define AB8500_INT_GPIO25R 49 /* not 8505 */
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#define AB8500_INT_GPIO36R 50 /* not 8505/9540 */
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#define AB8500_INT_GPIO37R 51 /* not 8505/9540 */
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#define AB8500_INT_GPIO38R 52 /* not 8505/9540 */
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#define AB8500_INT_GPIO39R 53 /* not 8505/9540 */
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#define AB8500_INT_GPIO40R 54
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#define AB8500_INT_GPIO41R 55
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#define AB8500_INT_GPIO6F 56
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#define AB8500_INT_GPIO7F 57
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#define AB8500_INT_GPIO8F 58
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#define AB8500_INT_GPIO9F 59
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/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
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#define AB8500_INT_GPIO6F 56 /* not 8505/9540 */
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#define AB8500_INT_GPIO7F 57 /* not 8505/9540 */
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#define AB8500_INT_GPIO8F 58 /* not 8505/9540 */
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#define AB8500_INT_GPIO9F 59 /* not 8505/9540 */
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#define AB8500_INT_GPIO10F 60
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#define AB8500_INT_GPIO11F 61
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#define AB8500_INT_GPIO12F 62
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#define AB8500_INT_GPIO12F 62 /* not 8505 */
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#define AB8500_INT_GPIO13F 63
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#define AB8500_INT_GPIO24F 64
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#define AB8500_INT_GPIO25F 65
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#define AB8500_INT_GPIO36F 66
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#define AB8500_INT_GPIO37F 67
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#define AB8500_INT_GPIO38F 68
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#define AB8500_INT_GPIO39F 69
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/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
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#define AB8500_INT_GPIO24F 64 /* not 8505 */
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#define AB8500_INT_GPIO25F 65 /* not 8505 */
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#define AB8500_INT_GPIO36F 66 /* not 8505/9540 */
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#define AB8500_INT_GPIO37F 67 /* not 8505/9540 */
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#define AB8500_INT_GPIO38F 68 /* not 8505/9540 */
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#define AB8500_INT_GPIO39F 69 /* not 8505/9540 */
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#define AB8500_INT_GPIO40F 70
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#define AB8500_INT_GPIO41F 71
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/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
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#define AB8500_INT_ADP_SOURCE_ERROR 72
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#define AB8500_INT_ADP_SINK_ERROR 73
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#define AB8500_INT_ADP_PROBE_PLUG 74
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@@ -116,30 +149,67 @@ struct device;
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#define AB8500_INT_ADP_SENSE_OFF 76
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#define AB8500_INT_USB_PHY_POWER_ERR 78
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#define AB8500_INT_USB_LINK_STATUS 79
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/* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */
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#define AB8500_INT_BTEMP_LOW 80
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#define AB8500_INT_BTEMP_LOW_MEDIUM 81
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#define AB8500_INT_BTEMP_MEDIUM_HIGH 82
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#define AB8500_INT_BTEMP_HIGH 83
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#define AB8500_INT_USB_CHARGER_NOT_OK 89
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/* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */
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#define AB8500_INT_SRP_DETECT 88
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#define AB8500_INT_USB_CHARGER_NOT_OKR 89
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#define AB8500_INT_ID_WAKEUP_R 90
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#define AB8500_INT_ID_DET_R1R 92
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#define AB8500_INT_ID_DET_R2R 93
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#define AB8500_INT_ID_DET_R3R 94
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#define AB8500_INT_ID_DET_R4R 95
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/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
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#define AB8500_INT_ID_WAKEUP_F 96
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#define AB8500_INT_ID_DET_R1F 98
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#define AB8500_INT_ID_DET_R2F 99
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#define AB8500_INT_ID_DET_R3F 100
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#define AB8500_INT_ID_DET_R4F 101
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#define AB8500_INT_USB_CHG_DET_DONE 102
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#define AB8500_INT_CHAUTORESTARTAFTSEC 102
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#define AB8500_INT_CHSTOPBYSEC 103
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/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
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#define AB8500_INT_USB_CH_TH_PROT_F 104
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#define AB8500_INT_USB_CH_TH_PROT_R 105
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#define AB8500_INT_MAIN_CH_TH_PROT_F 106
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#define AB8500_INT_MAIN_CH_TH_PROT_R 107
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#define AB8500_INT_USB_CHARGER_NOT_OKF 111
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#define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */
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#define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */
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#define AB8500_INT_CHCURLIMNOHSCHIRP 109
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#define AB8500_INT_CHCURLIMHSCHIRP 110
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#define AB8500_INT_XTAL32K_KO 111
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/* Definitions for AB9540 */
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/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
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#define AB9540_INT_GPIO50R 113
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#define AB9540_INT_GPIO51R 114 /* not 8505 */
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#define AB9540_INT_GPIO52R 115
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#define AB9540_INT_GPIO53R 116
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#define AB9540_INT_GPIO54R 117 /* not 8505 */
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#define AB9540_INT_IEXT_CH_RF_BFN_R 118
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#define AB9540_INT_IEXT_CH_RF_BFN_F 119
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/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
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#define AB9540_INT_GPIO50F 121
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#define AB9540_INT_GPIO51F 122 /* not 8505 */
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#define AB9540_INT_GPIO52F 123
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#define AB9540_INT_GPIO53F 124
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#define AB9540_INT_GPIO54F 125 /* not 8505 */
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/*
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* AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
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* entire platform. This is a "compile time" constant so this must be set to
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* the largest possible value that may be encountered with different AB SOCs.
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* Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
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* which is larger.
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*/
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#define AB8500_NR_IRQS 112
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#define AB8505_NR_IRQS 128
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#define AB9540_NR_IRQS 128
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/* This is set to the roof of any AB8500 chip variant IRQ counts */
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#define AB8500_MAX_NR_IRQS AB9540_NR_IRQS
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#define AB8500_NUM_IRQ_REGS 14
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#define AB9540_NUM_IRQ_REGS 17
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/**
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* struct ab8500 - ab8500 internal structure
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@@ -147,13 +217,18 @@ struct device;
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* @lock: read/write operations lock
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* @irq_lock: genirq bus lock
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* @irq: irq line
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* @version: chip version id (e.g. ab8500 or ab9540)
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* @chip_id: chip revision id
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* @write: register write
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* @write_masked: masked register write
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* @read: register read
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* @rx_buf: rx buf for SPI
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* @tx_buf: tx buf for SPI
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* @mask: cache of IRQ regs for bus lock
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* @oldmask: cache of previous IRQ regs for bus lock
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* @mask_size: Actual number of valid entries in mask[], oldmask[] and
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* irq_reg_offset
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* @irq_reg_offset: Array of offsets into IRQ registers
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*/
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struct ab8500 {
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struct device *dev;
|
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@@ -162,16 +237,20 @@ struct ab8500 {
|
||||
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int irq_base;
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int irq;
|
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enum ab8500_version version;
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u8 chip_id;
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int (*write) (struct ab8500 *a8500, u16 addr, u8 data);
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int (*read) (struct ab8500 *a8500, u16 addr);
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int (*write)(struct ab8500 *ab8500, u16 addr, u8 data);
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int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data);
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int (*read)(struct ab8500 *ab8500, u16 addr);
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unsigned long tx_buf[4];
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unsigned long rx_buf[4];
|
||||
|
||||
u8 mask[AB8500_NUM_IRQ_REGS];
|
||||
u8 oldmask[AB8500_NUM_IRQ_REGS];
|
||||
u8 *mask;
|
||||
u8 *oldmask;
|
||||
int mask_size;
|
||||
const int *irq_reg_offset;
|
||||
};
|
||||
|
||||
struct regulator_reg_init;
|
||||
@@ -197,7 +276,52 @@ struct ab8500_platform_data {
|
||||
struct ab8500_gpio_platform_data *gpio;
|
||||
};
|
||||
|
||||
extern int __devinit ab8500_init(struct ab8500 *ab8500);
|
||||
extern int __devinit ab8500_init(struct ab8500 *ab8500,
|
||||
enum ab8500_version version);
|
||||
extern int __devexit ab8500_exit(struct ab8500 *ab8500);
|
||||
|
||||
static inline int is_ab8500(struct ab8500 *ab)
|
||||
{
|
||||
return ab->version == AB8500_VERSION_AB8500;
|
||||
}
|
||||
|
||||
static inline int is_ab8505(struct ab8500 *ab)
|
||||
{
|
||||
return ab->version == AB8500_VERSION_AB8505;
|
||||
}
|
||||
|
||||
static inline int is_ab9540(struct ab8500 *ab)
|
||||
{
|
||||
return ab->version == AB8500_VERSION_AB9540;
|
||||
}
|
||||
|
||||
static inline int is_ab8540(struct ab8500 *ab)
|
||||
{
|
||||
return ab->version == AB8500_VERSION_AB8540;
|
||||
}
|
||||
|
||||
/* exclude also ab8505, ab9540... */
|
||||
static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab)
|
||||
{
|
||||
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0));
|
||||
}
|
||||
|
||||
/* exclude also ab8505, ab9540... */
|
||||
static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab)
|
||||
{
|
||||
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1));
|
||||
}
|
||||
|
||||
/* exclude also ab8505, ab9540... */
|
||||
static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
|
||||
{
|
||||
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
|
||||
}
|
||||
|
||||
/* exclude also ab8505, ab9540... */
|
||||
static inline int is_ab8500_2p0(struct ab8500 *ab)
|
||||
{
|
||||
return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
|
||||
}
|
||||
|
||||
#endif /* MFD_AB8500_H */
|
||||
|
||||
Reference in New Issue
Block a user