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MIPS: Add perf counter feature

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Add CPU feature for standard MIPS r2 performance counters, as determined
by the Config1.PC bit. Both perf_events and oprofile probe this bit, so
lets combine the probing and change both to use cpu_has_perf.

This will also be used for VZ support in KVM to know whether performance
counters exist which can be exposed to guests.

[ralf@linux-mips.org: resolve conflict.]

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Robert Richter <rric@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: oprofile-list@lists.sf.net
Patchwork: https://patchwork.linux-mips.org/patch/13226/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
James Hogan
2016-05-11 13:50:53 +01:00
committed by Ralf Baechle
parent f18bdfa191
commit 30228c40f0
5 changed files with 9 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/mips/include/asm/cpu-features.h
View File

@@ -454,4 +454,8 @@
# define cpu_has_contextconfig (cpu_data[0].options & MIPS_CPU_CTXTC) # define cpu_has_contextconfig (cpu_data[0].options & MIPS_CPU_CTXTC)
#endif #endif
#ifndef cpu_has_perf
# define cpu_has_perf (cpu_data[0].options & MIPS_CPU_PERF)
#endif
#endif /* __ASM_CPU_FEATURES_H */ #endif /* __ASM_CPU_FEATURES_H */

1
arch/mips/include/asm/cpu.h
View File

@@ -408,6 +408,7 @@ enum cpu_type_enum {
#define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */ #define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */
#define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */ #define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */
#define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */ #define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */
#define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */
/* /*
* CPU ASE encodings * CPU ASE encodings

2
arch/mips/kernel/cpu-probe.c
View File

@@ -648,6 +648,8 @@ static inline unsigned int decode_config1(struct cpuinfo_mips *c)
if (config1 & MIPS_CONF1_MD) if (config1 & MIPS_CONF1_MD)
c->ases |= MIPS_ASE_MDMX; c->ases |= MIPS_ASE_MDMX;
if (config1 & MIPS_CONF1_PC)
c->options |= MIPS_CPU_PERF;
if (config1 & MIPS_CONF1_WR) if (config1 & MIPS_CONF1_WR)
c->options |= MIPS_CPU_WATCH; c->options |= MIPS_CPU_WATCH;
if (config1 & MIPS_CONF1_CA) if (config1 & MIPS_CONF1_CA)

4
arch/mips/kernel/perf_event_mipsxx.c
View File

@@ -101,8 +101,6 @@ struct mips_pmu {
static struct mips_pmu mipspmu; static struct mips_pmu mipspmu;
#define M_CONFIG1_PC (1 << 4)
#define M_PERFCTL_EXL (1 << 0) #define M_PERFCTL_EXL (1 << 0)
#define M_PERFCTL_KERNEL (1 << 1) #define M_PERFCTL_KERNEL (1 << 1)
#define M_PERFCTL_SUPERVISOR (1 << 2) #define M_PERFCTL_SUPERVISOR (1 << 2)
@@ -754,7 +752,7 @@ static void handle_associated_event(struct cpu_hw_events *cpuc,
static int __n_counters(void) static int __n_counters(void)
{ {
if (!(read_c0_config1() & M_CONFIG1_PC)) if (!cpu_has_perf)
return 0; return 0;
if (!(read_c0_perfctrl0() & M_PERFCTL_MORE)) if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
return 1; return 1;

4
arch/mips/oprofile/op_model_mipsxx.c
View File

@@ -269,11 +269,9 @@ static int mipsxx_perfcount_handler(void)
return handled; return handled;
} }
#define M_CONFIG1_PC (1 << 4)
static inline int __n_counters(void) static inline int __n_counters(void)
{ {
if (!(read_c0_config1() & M_CONFIG1_PC)) if (!cpu_has_perf)
return 0; return 0;
if (!(read_c0_perfctrl0() & M_PERFCTL_MORE)) if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
return 1; return 1;