Merge tag 'mvebu-fixes-5.0-2' of git://git.infradead.org/linux-mvebu into arm/fixes

mvebu fixes for 5.0 (part 2)

Fix PHY reset signal on clearfog gt 8K (Armada 8040 based)
Fix NAND description on Armada XP boards which was broken since a few
release

* tag 'mvebu-fixes-5.0-2' of git://git.infradead.org/linux-mvebu:
  arm64: dts: clearfog-gt-8k: fix SGMII PHY reset signal
  ARM: dts: armada-xp: fix Armada XP boards NAND description

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2019-02-22 14:57:27 +01:00
4 changed files with 69 additions and 61 deletions

View File

@@ -144,11 +144,13 @@
status = "okay"; status = "okay";
}; };
nand@d0000 { nand-controller@d0000 {
status = "okay"; status = "okay";
nand@0 {
reg = <0>;
label = "pxa3xx_nand-0"; label = "pxa3xx_nand-0";
num-cs = <1>; nand-rb = <0>;
marvell,nand-keep-config;
nand-on-flash-bbt; nand-on-flash-bbt;
partitions { partitions {
@@ -167,7 +169,7 @@
partition@1000000 { partition@1000000 {
label = "Filesystem"; label = "Filesystem";
reg = <0x1000000 0x3f000000>; reg = <0x1000000 0x3f000000>;
};
}; };
}; };
}; };

View File

@@ -160,14 +160,17 @@
status = "okay"; status = "okay";
}; };
nand@d0000 { nand-controller@d0000 {
status = "okay"; status = "okay";
nand@0 {
reg = <0>;
label = "pxa3xx_nand-0"; label = "pxa3xx_nand-0";
num-cs = <1>; nand-rb = <0>;
marvell,nand-keep-config;
nand-on-flash-bbt; nand-on-flash-bbt;
}; };
}; };
};
bm-bppi { bm-bppi {
status = "okay"; status = "okay";

View File

@@ -81,11 +81,13 @@
}; };
nand@d0000 { nand-controller@d0000 {
status = "okay"; status = "okay";
nand@0 {
reg = <0>;
label = "pxa3xx_nand-0"; label = "pxa3xx_nand-0";
num-cs = <1>; nand-rb = <0>;
marvell,nand-keep-config;
nand-on-flash-bbt; nand-on-flash-bbt;
partitions { partitions {
@@ -129,6 +131,7 @@
}; };
}; };
}; };
};
gpio-keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";

View File

@@ -351,7 +351,7 @@
reg = <0>; reg = <0>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&cp0_copper_eth_phy_reset>; pinctrl-0 = <&cp0_copper_eth_phy_reset>;
reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>; reset-assert-us = <10000>;
}; };