Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-imx' into clk-next
- Qualcomm QCS404 CDSP clk support - Qualcomm QCS404 Turing clk support - Mediatek MT8183 clock support - Mediatek MT8516 clock support - Milbeaut M10V clk controller support * clk-renesas: clk: renesas: rcar-gen3: Remove unused variable clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value clk: renesas: r8a77980: Fix RPC-IF module clock's parent clk: renesas: rcar-gen3: Rename DRIF clocks clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC clk: renesas: rcar-gen3: Correct parent clock of HS-USB clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI clk: renesas: r8a774c0: Add Z2 clock clk: renesas: r8a77990: Add Z2 clock clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents math64: New DIV64_U64_ROUND_CLOSEST helper clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor clk: renesas: r9a06g032: Add missing PCI USB clock clk: renesas: r7s9210: Always use readl() clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register() * clk-qcom: clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998 clk: qcom: Add QCS404 TuringCC clk: qcom: branch: Add AON clock ops dt-bindings: clock: Introduce Qualcomm Turing Clock controller clk: qcom: gcc-qcs404: Add CDSP related clocks and resets * clk-mtk: clk: mediatek: add clock driver for MT8516 dt-bindings: mediatek: apmixedsys: add support for MT8516 dt-bindings: mediatek: infracfg: add support for MT8516 dt-bindings: mediatek: topckgen: add support for MT8516 clk: mediatek: Allow changing PLL rate when it is off clk: mediatek: Add MT8183 clock support clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data clk: mediatek: Add dt-bindings for MT8183 clocks dt-bindings: ARM: Mediatek: Document bindings for MT8183 clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data clk: mediatek: Add new clkmux register API clk: mediatek: Disable tuner_en before change PLL rate * clk-milbeaut: clock: milbeaut: Add Milbeaut M10V clock controller dt-bindings: clock: milbeaut: add Milbeaut clock description * clk-imx: clk: imx: correct pfdv2 gate_bit/vld_bit operations clk: imx: clk-pllv3: mark expected switch fall-throughs clk: imx8mq: Add dsi_ipg_div clk: imx: pllv4: add fractional-N pll support clk: imx: keep uart clock on during system boot clk: imx: correct i.MX7D AV PLL num/denom offset clk: imx6sll: Fix mispelling uart4_serial as serail clk: imx: pll14xx: drop unused variable clk: imx: rename clk-imx51-imx53.c to clk-imx5.c clk: imx5: Fix i.MX50 ESDHC clock registers clk: imx5: Fix i.MX50 mainbus clock registers clk: imx: Remove unused imx_get_clk_hw_fixed dt-bindings: clock: imx7ulp: remove SNVS clock clk: imx7ulp: remove snvs clock
This commit is contained in:
Stephen Boyd
@@ -65,7 +65,6 @@
|
||||
#define IMX7ULP_CLK_FLEXBUS 2
|
||||
#define IMX7ULP_CLK_SEMA42_1 3
|
||||
#define IMX7ULP_CLK_DMA_MUX1 4
|
||||
#define IMX7ULP_CLK_SNVS 5
|
||||
#define IMX7ULP_CLK_CAAM 6
|
||||
#define IMX7ULP_CLK_LPTPM4 7
|
||||
#define IMX7ULP_CLK_LPTPM5 8
|
||||
|
||||
422
include/dt-bindings/clock/mt8183-clk.h
Normal file
422
include/dt-bindings/clock/mt8183-clk.h
Normal file
@@ -0,0 +1,422 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2018 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MT8183_H
|
||||
#define _DT_BINDINGS_CLK_MT8183_H
|
||||
|
||||
/* APMIXED */
|
||||
#define CLK_APMIXED_ARMPLL_LL 0
|
||||
#define CLK_APMIXED_ARMPLL_L 1
|
||||
#define CLK_APMIXED_CCIPLL 2
|
||||
#define CLK_APMIXED_MAINPLL 3
|
||||
#define CLK_APMIXED_UNIV2PLL 4
|
||||
#define CLK_APMIXED_MSDCPLL 5
|
||||
#define CLK_APMIXED_MMPLL 6
|
||||
#define CLK_APMIXED_MFGPLL 7
|
||||
#define CLK_APMIXED_TVDPLL 8
|
||||
#define CLK_APMIXED_APLL1 9
|
||||
#define CLK_APMIXED_APLL2 10
|
||||
#define CLK_APMIXED_SSUSB_26M 11
|
||||
#define CLK_APMIXED_APPLL_26M 12
|
||||
#define CLK_APMIXED_MIPIC0_26M 13
|
||||
#define CLK_APMIXED_MDPLLGP_26M 14
|
||||
#define CLK_APMIXED_MMSYS_26M 15
|
||||
#define CLK_APMIXED_UFS_26M 16
|
||||
#define CLK_APMIXED_MIPIC1_26M 17
|
||||
#define CLK_APMIXED_MEMPLL_26M 18
|
||||
#define CLK_APMIXED_CLKSQ_LVPLL_26M 19
|
||||
#define CLK_APMIXED_MIPID0_26M 20
|
||||
#define CLK_APMIXED_MIPID1_26M 21
|
||||
#define CLK_APMIXED_NR_CLK 22
|
||||
|
||||
/* TOPCKGEN */
|
||||
#define CLK_TOP_MUX_AXI 0
|
||||
#define CLK_TOP_MUX_MM 1
|
||||
#define CLK_TOP_MUX_CAM 2
|
||||
#define CLK_TOP_MUX_MFG 3
|
||||
#define CLK_TOP_MUX_CAMTG 4
|
||||
#define CLK_TOP_MUX_UART 5
|
||||
#define CLK_TOP_MUX_SPI 6
|
||||
#define CLK_TOP_MUX_MSDC50_0_HCLK 7
|
||||
#define CLK_TOP_MUX_MSDC50_0 8
|
||||
#define CLK_TOP_MUX_MSDC30_1 9
|
||||
#define CLK_TOP_MUX_MSDC30_2 10
|
||||
#define CLK_TOP_MUX_AUDIO 11
|
||||
#define CLK_TOP_MUX_AUD_INTBUS 12
|
||||
#define CLK_TOP_MUX_FPWRAP_ULPOSC 13
|
||||
#define CLK_TOP_MUX_SCP 14
|
||||
#define CLK_TOP_MUX_ATB 15
|
||||
#define CLK_TOP_MUX_SSPM 16
|
||||
#define CLK_TOP_MUX_DPI0 17
|
||||
#define CLK_TOP_MUX_SCAM 18
|
||||
#define CLK_TOP_MUX_AUD_1 19
|
||||
#define CLK_TOP_MUX_AUD_2 20
|
||||
#define CLK_TOP_MUX_DISP_PWM 21
|
||||
#define CLK_TOP_MUX_SSUSB_TOP_XHCI 22
|
||||
#define CLK_TOP_MUX_USB_TOP 23
|
||||
#define CLK_TOP_MUX_SPM 24
|
||||
#define CLK_TOP_MUX_I2C 25
|
||||
#define CLK_TOP_MUX_F52M_MFG 26
|
||||
#define CLK_TOP_MUX_SENINF 27
|
||||
#define CLK_TOP_MUX_DXCC 28
|
||||
#define CLK_TOP_MUX_CAMTG2 29
|
||||
#define CLK_TOP_MUX_AUD_ENG1 30
|
||||
#define CLK_TOP_MUX_AUD_ENG2 31
|
||||
#define CLK_TOP_MUX_FAES_UFSFDE 32
|
||||
#define CLK_TOP_MUX_FUFS 33
|
||||
#define CLK_TOP_MUX_IMG 34
|
||||
#define CLK_TOP_MUX_DSP 35
|
||||
#define CLK_TOP_MUX_DSP1 36
|
||||
#define CLK_TOP_MUX_DSP2 37
|
||||
#define CLK_TOP_MUX_IPU_IF 38
|
||||
#define CLK_TOP_MUX_CAMTG3 39
|
||||
#define CLK_TOP_MUX_CAMTG4 40
|
||||
#define CLK_TOP_MUX_PMICSPI 41
|
||||
#define CLK_TOP_SYSPLL_CK 42
|
||||
#define CLK_TOP_SYSPLL_D2 43
|
||||
#define CLK_TOP_SYSPLL_D3 44
|
||||
#define CLK_TOP_SYSPLL_D5 45
|
||||
#define CLK_TOP_SYSPLL_D7 46
|
||||
#define CLK_TOP_SYSPLL_D2_D2 47
|
||||
#define CLK_TOP_SYSPLL_D2_D4 48
|
||||
#define CLK_TOP_SYSPLL_D2_D8 49
|
||||
#define CLK_TOP_SYSPLL_D2_D16 50
|
||||
#define CLK_TOP_SYSPLL_D3_D2 51
|
||||
#define CLK_TOP_SYSPLL_D3_D4 52
|
||||
#define CLK_TOP_SYSPLL_D3_D8 53
|
||||
#define CLK_TOP_SYSPLL_D5_D2 54
|
||||
#define CLK_TOP_SYSPLL_D5_D4 55
|
||||
#define CLK_TOP_SYSPLL_D7_D2 56
|
||||
#define CLK_TOP_SYSPLL_D7_D4 57
|
||||
#define CLK_TOP_UNIVPLL_CK 58
|
||||
#define CLK_TOP_UNIVPLL_D2 59
|
||||
#define CLK_TOP_UNIVPLL_D3 60
|
||||
#define CLK_TOP_UNIVPLL_D5 61
|
||||
#define CLK_TOP_UNIVPLL_D7 62
|
||||
#define CLK_TOP_UNIVPLL_D2_D2 63
|
||||
#define CLK_TOP_UNIVPLL_D2_D4 64
|
||||
#define CLK_TOP_UNIVPLL_D2_D8 65
|
||||
#define CLK_TOP_UNIVPLL_D3_D2 66
|
||||
#define CLK_TOP_UNIVPLL_D3_D4 67
|
||||
#define CLK_TOP_UNIVPLL_D3_D8 68
|
||||
#define CLK_TOP_UNIVPLL_D5_D2 69
|
||||
#define CLK_TOP_UNIVPLL_D5_D4 70
|
||||
#define CLK_TOP_UNIVPLL_D5_D8 71
|
||||
#define CLK_TOP_APLL1_CK 72
|
||||
#define CLK_TOP_APLL1_D2 73
|
||||
#define CLK_TOP_APLL1_D4 74
|
||||
#define CLK_TOP_APLL1_D8 75
|
||||
#define CLK_TOP_APLL2_CK 76
|
||||
#define CLK_TOP_APLL2_D2 77
|
||||
#define CLK_TOP_APLL2_D4 78
|
||||
#define CLK_TOP_APLL2_D8 79
|
||||
#define CLK_TOP_TVDPLL_CK 80
|
||||
#define CLK_TOP_TVDPLL_D2 81
|
||||
#define CLK_TOP_TVDPLL_D4 82
|
||||
#define CLK_TOP_TVDPLL_D8 83
|
||||
#define CLK_TOP_TVDPLL_D16 84
|
||||
#define CLK_TOP_MSDCPLL_CK 85
|
||||
#define CLK_TOP_MSDCPLL_D2 86
|
||||
#define CLK_TOP_MSDCPLL_D4 87
|
||||
#define CLK_TOP_MSDCPLL_D8 88
|
||||
#define CLK_TOP_MSDCPLL_D16 89
|
||||
#define CLK_TOP_AD_OSC_CK 90
|
||||
#define CLK_TOP_OSC_D2 91
|
||||
#define CLK_TOP_OSC_D4 92
|
||||
#define CLK_TOP_OSC_D8 93
|
||||
#define CLK_TOP_OSC_D16 94
|
||||
#define CLK_TOP_F26M_CK_D2 95
|
||||
#define CLK_TOP_MFGPLL_CK 96
|
||||
#define CLK_TOP_UNIVP_192M_CK 97
|
||||
#define CLK_TOP_UNIVP_192M_D2 98
|
||||
#define CLK_TOP_UNIVP_192M_D4 99
|
||||
#define CLK_TOP_UNIVP_192M_D8 100
|
||||
#define CLK_TOP_UNIVP_192M_D16 101
|
||||
#define CLK_TOP_UNIVP_192M_D32 102
|
||||
#define CLK_TOP_MMPLL_CK 103
|
||||
#define CLK_TOP_MMPLL_D4 104
|
||||
#define CLK_TOP_MMPLL_D4_D2 105
|
||||
#define CLK_TOP_MMPLL_D4_D4 106
|
||||
#define CLK_TOP_MMPLL_D5 107
|
||||
#define CLK_TOP_MMPLL_D5_D2 108
|
||||
#define CLK_TOP_MMPLL_D5_D4 109
|
||||
#define CLK_TOP_MMPLL_D6 110
|
||||
#define CLK_TOP_MMPLL_D7 111
|
||||
#define CLK_TOP_CLK26M 112
|
||||
#define CLK_TOP_CLK13M 113
|
||||
#define CLK_TOP_ULPOSC 114
|
||||
#define CLK_TOP_UNIVP_192M 115
|
||||
#define CLK_TOP_MUX_APLL_I2S0 116
|
||||
#define CLK_TOP_MUX_APLL_I2S1 117
|
||||
#define CLK_TOP_MUX_APLL_I2S2 118
|
||||
#define CLK_TOP_MUX_APLL_I2S3 119
|
||||
#define CLK_TOP_MUX_APLL_I2S4 120
|
||||
#define CLK_TOP_MUX_APLL_I2S5 121
|
||||
#define CLK_TOP_APLL12_DIV0 122
|
||||
#define CLK_TOP_APLL12_DIV1 123
|
||||
#define CLK_TOP_APLL12_DIV2 124
|
||||
#define CLK_TOP_APLL12_DIV3 125
|
||||
#define CLK_TOP_APLL12_DIV4 126
|
||||
#define CLK_TOP_APLL12_DIVB 127
|
||||
#define CLK_TOP_UNIVPLL 128
|
||||
#define CLK_TOP_ARMPLL_DIV_PLL1 129
|
||||
#define CLK_TOP_ARMPLL_DIV_PLL2 130
|
||||
#define CLK_TOP_UNIVPLL_D3_D16 131
|
||||
#define CLK_TOP_NR_CLK 132
|
||||
|
||||
/* CAMSYS */
|
||||
#define CLK_CAM_LARB6 0
|
||||
#define CLK_CAM_DFP_VAD 1
|
||||
#define CLK_CAM_CAM 2
|
||||
#define CLK_CAM_CAMTG 3
|
||||
#define CLK_CAM_SENINF 4
|
||||
#define CLK_CAM_CAMSV0 5
|
||||
#define CLK_CAM_CAMSV1 6
|
||||
#define CLK_CAM_CAMSV2 7
|
||||
#define CLK_CAM_CCU 8
|
||||
#define CLK_CAM_LARB3 9
|
||||
#define CLK_CAM_NR_CLK 10
|
||||
|
||||
/* INFRACFG_AO */
|
||||
#define CLK_INFRA_PMIC_TMR 0
|
||||
#define CLK_INFRA_PMIC_AP 1
|
||||
#define CLK_INFRA_PMIC_MD 2
|
||||
#define CLK_INFRA_PMIC_CONN 3
|
||||
#define CLK_INFRA_SCPSYS 4
|
||||
#define CLK_INFRA_SEJ 5
|
||||
#define CLK_INFRA_APXGPT 6
|
||||
#define CLK_INFRA_ICUSB 7
|
||||
#define CLK_INFRA_GCE 8
|
||||
#define CLK_INFRA_THERM 9
|
||||
#define CLK_INFRA_I2C0 10
|
||||
#define CLK_INFRA_I2C1 11
|
||||
#define CLK_INFRA_I2C2 12
|
||||
#define CLK_INFRA_I2C3 13
|
||||
#define CLK_INFRA_PWM_HCLK 14
|
||||
#define CLK_INFRA_PWM1 15
|
||||
#define CLK_INFRA_PWM2 16
|
||||
#define CLK_INFRA_PWM3 17
|
||||
#define CLK_INFRA_PWM4 18
|
||||
#define CLK_INFRA_PWM 19
|
||||
#define CLK_INFRA_UART0 20
|
||||
#define CLK_INFRA_UART1 21
|
||||
#define CLK_INFRA_UART2 22
|
||||
#define CLK_INFRA_UART3 23
|
||||
#define CLK_INFRA_GCE_26M 24
|
||||
#define CLK_INFRA_CQ_DMA_FPC 25
|
||||
#define CLK_INFRA_BTIF 26
|
||||
#define CLK_INFRA_SPI0 27
|
||||
#define CLK_INFRA_MSDC0 28
|
||||
#define CLK_INFRA_MSDC1 29
|
||||
#define CLK_INFRA_MSDC2 30
|
||||
#define CLK_INFRA_MSDC0_SCK 31
|
||||
#define CLK_INFRA_DVFSRC 32
|
||||
#define CLK_INFRA_GCPU 33
|
||||
#define CLK_INFRA_TRNG 34
|
||||
#define CLK_INFRA_AUXADC 35
|
||||
#define CLK_INFRA_CPUM 36
|
||||
#define CLK_INFRA_CCIF1_AP 37
|
||||
#define CLK_INFRA_CCIF1_MD 38
|
||||
#define CLK_INFRA_AUXADC_MD 39
|
||||
#define CLK_INFRA_MSDC1_SCK 40
|
||||
#define CLK_INFRA_MSDC2_SCK 41
|
||||
#define CLK_INFRA_AP_DMA 42
|
||||
#define CLK_INFRA_XIU 43
|
||||
#define CLK_INFRA_DEVICE_APC 44
|
||||
#define CLK_INFRA_CCIF_AP 45
|
||||
#define CLK_INFRA_DEBUGSYS 46
|
||||
#define CLK_INFRA_AUDIO 47
|
||||
#define CLK_INFRA_CCIF_MD 48
|
||||
#define CLK_INFRA_DXCC_SEC_CORE 49
|
||||
#define CLK_INFRA_DXCC_AO 50
|
||||
#define CLK_INFRA_DRAMC_F26M 51
|
||||
#define CLK_INFRA_IRTX 52
|
||||
#define CLK_INFRA_DISP_PWM 53
|
||||
#define CLK_INFRA_CLDMA_BCLK 54
|
||||
#define CLK_INFRA_AUDIO_26M_BCLK 55
|
||||
#define CLK_INFRA_SPI1 56
|
||||
#define CLK_INFRA_I2C4 57
|
||||
#define CLK_INFRA_MODEM_TEMP_SHARE 58
|
||||
#define CLK_INFRA_SPI2 59
|
||||
#define CLK_INFRA_SPI3 60
|
||||
#define CLK_INFRA_UNIPRO_SCK 61
|
||||
#define CLK_INFRA_UNIPRO_TICK 62
|
||||
#define CLK_INFRA_UFS_MP_SAP_BCLK 63
|
||||
#define CLK_INFRA_MD32_BCLK 64
|
||||
#define CLK_INFRA_SSPM 65
|
||||
#define CLK_INFRA_UNIPRO_MBIST 66
|
||||
#define CLK_INFRA_SSPM_BUS_HCLK 67
|
||||
#define CLK_INFRA_I2C5 68
|
||||
#define CLK_INFRA_I2C5_ARBITER 69
|
||||
#define CLK_INFRA_I2C5_IMM 70
|
||||
#define CLK_INFRA_I2C1_ARBITER 71
|
||||
#define CLK_INFRA_I2C1_IMM 72
|
||||
#define CLK_INFRA_I2C2_ARBITER 73
|
||||
#define CLK_INFRA_I2C2_IMM 74
|
||||
#define CLK_INFRA_SPI4 75
|
||||
#define CLK_INFRA_SPI5 76
|
||||
#define CLK_INFRA_CQ_DMA 77
|
||||
#define CLK_INFRA_UFS 78
|
||||
#define CLK_INFRA_AES_UFSFDE 79
|
||||
#define CLK_INFRA_UFS_TICK 80
|
||||
#define CLK_INFRA_MSDC0_SELF 81
|
||||
#define CLK_INFRA_MSDC1_SELF 82
|
||||
#define CLK_INFRA_MSDC2_SELF 83
|
||||
#define CLK_INFRA_SSPM_26M_SELF 84
|
||||
#define CLK_INFRA_SSPM_32K_SELF 85
|
||||
#define CLK_INFRA_UFS_AXI 86
|
||||
#define CLK_INFRA_I2C6 87
|
||||
#define CLK_INFRA_AP_MSDC0 88
|
||||
#define CLK_INFRA_MD_MSDC0 89
|
||||
#define CLK_INFRA_USB 90
|
||||
#define CLK_INFRA_DEVMPU_BCLK 91
|
||||
#define CLK_INFRA_CCIF2_AP 92
|
||||
#define CLK_INFRA_CCIF2_MD 93
|
||||
#define CLK_INFRA_CCIF3_AP 94
|
||||
#define CLK_INFRA_CCIF3_MD 95
|
||||
#define CLK_INFRA_SEJ_F13M 96
|
||||
#define CLK_INFRA_AES_BCLK 97
|
||||
#define CLK_INFRA_I2C7 98
|
||||
#define CLK_INFRA_I2C8 99
|
||||
#define CLK_INFRA_FBIST2FPC 100
|
||||
#define CLK_INFRA_NR_CLK 101
|
||||
|
||||
/* MFGCFG */
|
||||
#define CLK_MFG_BG3D 0
|
||||
#define CLK_MFG_NR_CLK 1
|
||||
|
||||
/* IMG */
|
||||
#define CLK_IMG_OWE 0
|
||||
#define CLK_IMG_WPE_B 1
|
||||
#define CLK_IMG_WPE_A 2
|
||||
#define CLK_IMG_MFB 3
|
||||
#define CLK_IMG_RSC 4
|
||||
#define CLK_IMG_DPE 5
|
||||
#define CLK_IMG_FDVT 6
|
||||
#define CLK_IMG_DIP 7
|
||||
#define CLK_IMG_LARB2 8
|
||||
#define CLK_IMG_LARB5 9
|
||||
#define CLK_IMG_NR_CLK 10
|
||||
|
||||
/* MMSYS_CONFIG */
|
||||
#define CLK_MM_SMI_COMMON 0
|
||||
#define CLK_MM_SMI_LARB0 1
|
||||
#define CLK_MM_SMI_LARB1 2
|
||||
#define CLK_MM_GALS_COMM0 3
|
||||
#define CLK_MM_GALS_COMM1 4
|
||||
#define CLK_MM_GALS_CCU2MM 5
|
||||
#define CLK_MM_GALS_IPU12MM 6
|
||||
#define CLK_MM_GALS_IMG2MM 7
|
||||
#define CLK_MM_GALS_CAM2MM 8
|
||||
#define CLK_MM_GALS_IPU2MM 9
|
||||
#define CLK_MM_MDP_DL_TXCK 10
|
||||
#define CLK_MM_IPU_DL_TXCK 11
|
||||
#define CLK_MM_MDP_RDMA0 12
|
||||
#define CLK_MM_MDP_RDMA1 13
|
||||
#define CLK_MM_MDP_RSZ0 14
|
||||
#define CLK_MM_MDP_RSZ1 15
|
||||
#define CLK_MM_MDP_TDSHP 16
|
||||
#define CLK_MM_MDP_WROT0 17
|
||||
#define CLK_MM_FAKE_ENG 18
|
||||
#define CLK_MM_DISP_OVL0 19
|
||||
#define CLK_MM_DISP_OVL0_2L 20
|
||||
#define CLK_MM_DISP_OVL1_2L 21
|
||||
#define CLK_MM_DISP_RDMA0 22
|
||||
#define CLK_MM_DISP_RDMA1 23
|
||||
#define CLK_MM_DISP_WDMA0 24
|
||||
#define CLK_MM_DISP_COLOR0 25
|
||||
#define CLK_MM_DISP_CCORR0 26
|
||||
#define CLK_MM_DISP_AAL0 27
|
||||
#define CLK_MM_DISP_GAMMA0 28
|
||||
#define CLK_MM_DISP_DITHER0 29
|
||||
#define CLK_MM_DISP_SPLIT 30
|
||||
#define CLK_MM_DSI0_MM 31
|
||||
#define CLK_MM_DSI0_IF 32
|
||||
#define CLK_MM_DPI_MM 33
|
||||
#define CLK_MM_DPI_IF 34
|
||||
#define CLK_MM_FAKE_ENG2 35
|
||||
#define CLK_MM_MDP_DL_RX 36
|
||||
#define CLK_MM_IPU_DL_RX 37
|
||||
#define CLK_MM_26M 38
|
||||
#define CLK_MM_MMSYS_R2Y 39
|
||||
#define CLK_MM_DISP_RSZ 40
|
||||
#define CLK_MM_MDP_WDMA0 41
|
||||
#define CLK_MM_MDP_AAL 42
|
||||
#define CLK_MM_MDP_CCORR 43
|
||||
#define CLK_MM_DBI_MM 44
|
||||
#define CLK_MM_DBI_IF 45
|
||||
#define CLK_MM_NR_CLK 46
|
||||
|
||||
/* VDEC_GCON */
|
||||
#define CLK_VDEC_VDEC 0
|
||||
#define CLK_VDEC_LARB1 1
|
||||
#define CLK_VDEC_NR_CLK 2
|
||||
|
||||
/* VENC_GCON */
|
||||
#define CLK_VENC_LARB 0
|
||||
#define CLK_VENC_VENC 1
|
||||
#define CLK_VENC_JPGENC 2
|
||||
#define CLK_VENC_NR_CLK 3
|
||||
|
||||
/* AUDIO */
|
||||
#define CLK_AUDIO_TML 0
|
||||
#define CLK_AUDIO_DAC_PREDIS 1
|
||||
#define CLK_AUDIO_DAC 2
|
||||
#define CLK_AUDIO_ADC 3
|
||||
#define CLK_AUDIO_APLL_TUNER 4
|
||||
#define CLK_AUDIO_APLL2_TUNER 5
|
||||
#define CLK_AUDIO_24M 6
|
||||
#define CLK_AUDIO_22M 7
|
||||
#define CLK_AUDIO_AFE 8
|
||||
#define CLK_AUDIO_I2S4 9
|
||||
#define CLK_AUDIO_I2S3 10
|
||||
#define CLK_AUDIO_I2S2 11
|
||||
#define CLK_AUDIO_I2S1 12
|
||||
#define CLK_AUDIO_PDN_ADDA6_ADC 13
|
||||
#define CLK_AUDIO_TDM 14
|
||||
#define CLK_AUDIO_NR_CLK 15
|
||||
|
||||
/* IPU_CONN */
|
||||
#define CLK_IPU_CONN_IPU 0
|
||||
#define CLK_IPU_CONN_AHB 1
|
||||
#define CLK_IPU_CONN_AXI 2
|
||||
#define CLK_IPU_CONN_ISP 3
|
||||
#define CLK_IPU_CONN_CAM_ADL 4
|
||||
#define CLK_IPU_CONN_IMG_ADL 5
|
||||
#define CLK_IPU_CONN_DAP_RX 6
|
||||
#define CLK_IPU_CONN_APB2AXI 7
|
||||
#define CLK_IPU_CONN_APB2AHB 8
|
||||
#define CLK_IPU_CONN_IPU_CAB1TO2 9
|
||||
#define CLK_IPU_CONN_IPU1_CAB1TO2 10
|
||||
#define CLK_IPU_CONN_IPU2_CAB1TO2 11
|
||||
#define CLK_IPU_CONN_CAB3TO3 12
|
||||
#define CLK_IPU_CONN_CAB2TO1 13
|
||||
#define CLK_IPU_CONN_CAB3TO1_SLICE 14
|
||||
#define CLK_IPU_CONN_NR_CLK 15
|
||||
|
||||
/* IPU_ADL */
|
||||
#define CLK_IPU_ADL_CABGEN 0
|
||||
#define CLK_IPU_ADL_NR_CLK 1
|
||||
|
||||
/* IPU_CORE0 */
|
||||
#define CLK_IPU_CORE0_JTAG 0
|
||||
#define CLK_IPU_CORE0_AXI 1
|
||||
#define CLK_IPU_CORE0_IPU 2
|
||||
#define CLK_IPU_CORE0_NR_CLK 3
|
||||
|
||||
/* IPU_CORE1 */
|
||||
#define CLK_IPU_CORE1_JTAG 0
|
||||
#define CLK_IPU_CORE1_AXI 1
|
||||
#define CLK_IPU_CORE1_IPU 2
|
||||
#define CLK_IPU_CORE1_NR_CLK 3
|
||||
|
||||
/* MCUCFG */
|
||||
#define CLK_MCU_MP0_SEL 0
|
||||
#define CLK_MCU_MP2_SEL 1
|
||||
#define CLK_MCU_BUS_SEL 2
|
||||
#define CLK_MCU_NR_CLK 3
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT8183_H */
|
||||
211
include/dt-bindings/clock/mt8516-clk.h
Normal file
211
include/dt-bindings/clock/mt8516-clk.h
Normal file
@@ -0,0 +1,211 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2019 MediaTek Inc.
|
||||
* Copyright (c) 2019 BayLibre, SAS.
|
||||
* Author: James Liao <jamesjj.liao@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MT8516_H
|
||||
#define _DT_BINDINGS_CLK_MT8516_H
|
||||
|
||||
/* APMIXEDSYS */
|
||||
|
||||
#define CLK_APMIXED_ARMPLL 0
|
||||
#define CLK_APMIXED_MAINPLL 1
|
||||
#define CLK_APMIXED_UNIVPLL 2
|
||||
#define CLK_APMIXED_MMPLL 3
|
||||
#define CLK_APMIXED_APLL1 4
|
||||
#define CLK_APMIXED_APLL2 5
|
||||
#define CLK_APMIXED_NR_CLK 6
|
||||
|
||||
/* INFRACFG */
|
||||
|
||||
#define CLK_IFR_MUX1_SEL 0
|
||||
#define CLK_IFR_ETH_25M_SEL 1
|
||||
#define CLK_IFR_I2C0_SEL 2
|
||||
#define CLK_IFR_I2C1_SEL 3
|
||||
#define CLK_IFR_I2C2_SEL 4
|
||||
#define CLK_IFR_NR_CLK 5
|
||||
|
||||
/* TOPCKGEN */
|
||||
|
||||
#define CLK_TOP_CLK_NULL 0
|
||||
#define CLK_TOP_I2S_INFRA_BCK 1
|
||||
#define CLK_TOP_MEMPLL 2
|
||||
#define CLK_TOP_DMPLL 3
|
||||
#define CLK_TOP_MAINPLL_D2 4
|
||||
#define CLK_TOP_MAINPLL_D4 5
|
||||
#define CLK_TOP_MAINPLL_D8 6
|
||||
#define CLK_TOP_MAINPLL_D16 7
|
||||
#define CLK_TOP_MAINPLL_D11 8
|
||||
#define CLK_TOP_MAINPLL_D22 9
|
||||
#define CLK_TOP_MAINPLL_D3 10
|
||||
#define CLK_TOP_MAINPLL_D6 11
|
||||
#define CLK_TOP_MAINPLL_D12 12
|
||||
#define CLK_TOP_MAINPLL_D5 13
|
||||
#define CLK_TOP_MAINPLL_D10 14
|
||||
#define CLK_TOP_MAINPLL_D20 15
|
||||
#define CLK_TOP_MAINPLL_D40 16
|
||||
#define CLK_TOP_MAINPLL_D7 17
|
||||
#define CLK_TOP_MAINPLL_D14 18
|
||||
#define CLK_TOP_UNIVPLL_D2 19
|
||||
#define CLK_TOP_UNIVPLL_D4 20
|
||||
#define CLK_TOP_UNIVPLL_D8 21
|
||||
#define CLK_TOP_UNIVPLL_D16 22
|
||||
#define CLK_TOP_UNIVPLL_D3 23
|
||||
#define CLK_TOP_UNIVPLL_D6 24
|
||||
#define CLK_TOP_UNIVPLL_D12 25
|
||||
#define CLK_TOP_UNIVPLL_D24 26
|
||||
#define CLK_TOP_UNIVPLL_D5 27
|
||||
#define CLK_TOP_UNIVPLL_D20 28
|
||||
#define CLK_TOP_MMPLL380M 29
|
||||
#define CLK_TOP_MMPLL_D2 30
|
||||
#define CLK_TOP_MMPLL_200M 31
|
||||
#define CLK_TOP_USB_PHY48M 32
|
||||
#define CLK_TOP_APLL1 33
|
||||
#define CLK_TOP_APLL1_D2 34
|
||||
#define CLK_TOP_APLL1_D4 35
|
||||
#define CLK_TOP_APLL1_D8 36
|
||||
#define CLK_TOP_APLL2 37
|
||||
#define CLK_TOP_APLL2_D2 38
|
||||
#define CLK_TOP_APLL2_D4 39
|
||||
#define CLK_TOP_APLL2_D8 40
|
||||
#define CLK_TOP_CLK26M 41
|
||||
#define CLK_TOP_CLK26M_D2 42
|
||||
#define CLK_TOP_AHB_INFRA_D2 43
|
||||
#define CLK_TOP_NFI1X 44
|
||||
#define CLK_TOP_ETH_D2 45
|
||||
#define CLK_TOP_THEM 46
|
||||
#define CLK_TOP_APDMA 47
|
||||
#define CLK_TOP_I2C0 48
|
||||
#define CLK_TOP_I2C1 49
|
||||
#define CLK_TOP_AUXADC1 50
|
||||
#define CLK_TOP_NFI 51
|
||||
#define CLK_TOP_NFIECC 52
|
||||
#define CLK_TOP_DEBUGSYS 53
|
||||
#define CLK_TOP_PWM 54
|
||||
#define CLK_TOP_UART0 55
|
||||
#define CLK_TOP_UART1 56
|
||||
#define CLK_TOP_BTIF 57
|
||||
#define CLK_TOP_USB 58
|
||||
#define CLK_TOP_FLASHIF_26M 59
|
||||
#define CLK_TOP_AUXADC2 60
|
||||
#define CLK_TOP_I2C2 61
|
||||
#define CLK_TOP_MSDC0 62
|
||||
#define CLK_TOP_MSDC1 63
|
||||
#define CLK_TOP_NFI2X 64
|
||||
#define CLK_TOP_PMICWRAP_AP 65
|
||||
#define CLK_TOP_SEJ 66
|
||||
#define CLK_TOP_MEMSLP_DLYER 67
|
||||
#define CLK_TOP_SPI 68
|
||||
#define CLK_TOP_APXGPT 69
|
||||
#define CLK_TOP_AUDIO 70
|
||||
#define CLK_TOP_PMICWRAP_MD 71
|
||||
#define CLK_TOP_PMICWRAP_CONN 72
|
||||
#define CLK_TOP_PMICWRAP_26M 73
|
||||
#define CLK_TOP_AUX_ADC 74
|
||||
#define CLK_TOP_AUX_TP 75
|
||||
#define CLK_TOP_MSDC2 76
|
||||
#define CLK_TOP_RBIST 77
|
||||
#define CLK_TOP_NFI_BUS 78
|
||||
#define CLK_TOP_GCE 79
|
||||
#define CLK_TOP_TRNG 80
|
||||
#define CLK_TOP_SEJ_13M 81
|
||||
#define CLK_TOP_AES 82
|
||||
#define CLK_TOP_PWM_B 83
|
||||
#define CLK_TOP_PWM1_FB 84
|
||||
#define CLK_TOP_PWM2_FB 85
|
||||
#define CLK_TOP_PWM3_FB 86
|
||||
#define CLK_TOP_PWM4_FB 87
|
||||
#define CLK_TOP_PWM5_FB 88
|
||||
#define CLK_TOP_USB_1P 89
|
||||
#define CLK_TOP_FLASHIF_FREERUN 90
|
||||
#define CLK_TOP_66M_ETH 91
|
||||
#define CLK_TOP_133M_ETH 92
|
||||
#define CLK_TOP_FETH_25M 93
|
||||
#define CLK_TOP_FETH_50M 94
|
||||
#define CLK_TOP_FLASHIF_AXI 95
|
||||
#define CLK_TOP_USBIF 96
|
||||
#define CLK_TOP_UART2 97
|
||||
#define CLK_TOP_BSI 98
|
||||
#define CLK_TOP_RG_SPINOR 99
|
||||
#define CLK_TOP_RG_MSDC2 100
|
||||
#define CLK_TOP_RG_ETH 101
|
||||
#define CLK_TOP_RG_AUD1 102
|
||||
#define CLK_TOP_RG_AUD2 103
|
||||
#define CLK_TOP_RG_AUD_ENGEN1 104
|
||||
#define CLK_TOP_RG_AUD_ENGEN2 105
|
||||
#define CLK_TOP_RG_I2C 106
|
||||
#define CLK_TOP_RG_PWM_INFRA 107
|
||||
#define CLK_TOP_RG_AUD_SPDIF_IN 108
|
||||
#define CLK_TOP_RG_UART2 109
|
||||
#define CLK_TOP_RG_BSI 110
|
||||
#define CLK_TOP_RG_DBG_ATCLK 111
|
||||
#define CLK_TOP_RG_NFIECC 112
|
||||
#define CLK_TOP_RG_APLL1_D2_EN 113
|
||||
#define CLK_TOP_RG_APLL1_D4_EN 114
|
||||
#define CLK_TOP_RG_APLL1_D8_EN 115
|
||||
#define CLK_TOP_RG_APLL2_D2_EN 116
|
||||
#define CLK_TOP_RG_APLL2_D4_EN 117
|
||||
#define CLK_TOP_RG_APLL2_D8_EN 118
|
||||
#define CLK_TOP_APLL12_DIV0 119
|
||||
#define CLK_TOP_APLL12_DIV1 120
|
||||
#define CLK_TOP_APLL12_DIV2 121
|
||||
#define CLK_TOP_APLL12_DIV3 122
|
||||
#define CLK_TOP_APLL12_DIV4 123
|
||||
#define CLK_TOP_APLL12_DIV4B 124
|
||||
#define CLK_TOP_APLL12_DIV5 125
|
||||
#define CLK_TOP_APLL12_DIV5B 126
|
||||
#define CLK_TOP_APLL12_DIV6 127
|
||||
#define CLK_TOP_UART0_SEL 128
|
||||
#define CLK_TOP_EMI_DDRPHY_SEL 129
|
||||
#define CLK_TOP_AHB_INFRA_SEL 130
|
||||
#define CLK_TOP_MSDC0_SEL 131
|
||||
#define CLK_TOP_UART1_SEL 132
|
||||
#define CLK_TOP_MSDC1_SEL 133
|
||||
#define CLK_TOP_PMICSPI_SEL 134
|
||||
#define CLK_TOP_QAXI_AUD26M_SEL 135
|
||||
#define CLK_TOP_AUD_INTBUS_SEL 136
|
||||
#define CLK_TOP_NFI2X_PAD_SEL 137
|
||||
#define CLK_TOP_NFI1X_PAD_SEL 138
|
||||
#define CLK_TOP_DDRPHYCFG_SEL 139
|
||||
#define CLK_TOP_USB_78M_SEL 140
|
||||
#define CLK_TOP_SPINOR_SEL 141
|
||||
#define CLK_TOP_MSDC2_SEL 142
|
||||
#define CLK_TOP_ETH_SEL 143
|
||||
#define CLK_TOP_AUD1_SEL 144
|
||||
#define CLK_TOP_AUD2_SEL 145
|
||||
#define CLK_TOP_AUD_ENGEN1_SEL 146
|
||||
#define CLK_TOP_AUD_ENGEN2_SEL 147
|
||||
#define CLK_TOP_I2C_SEL 148
|
||||
#define CLK_TOP_AUD_I2S0_M_SEL 149
|
||||
#define CLK_TOP_AUD_I2S1_M_SEL 150
|
||||
#define CLK_TOP_AUD_I2S2_M_SEL 151
|
||||
#define CLK_TOP_AUD_I2S3_M_SEL 152
|
||||
#define CLK_TOP_AUD_I2S4_M_SEL 153
|
||||
#define CLK_TOP_AUD_I2S5_M_SEL 154
|
||||
#define CLK_TOP_AUD_SPDIF_B_SEL 155
|
||||
#define CLK_TOP_PWM_SEL 156
|
||||
#define CLK_TOP_SPI_SEL 157
|
||||
#define CLK_TOP_AUD_SPDIFIN_SEL 158
|
||||
#define CLK_TOP_UART2_SEL 159
|
||||
#define CLK_TOP_BSI_SEL 160
|
||||
#define CLK_TOP_DBG_ATCLK_SEL 161
|
||||
#define CLK_TOP_CSW_NFIECC_SEL 162
|
||||
#define CLK_TOP_NFIECC_SEL 163
|
||||
#define CLK_TOP_APLL12_CK_DIV0 164
|
||||
#define CLK_TOP_APLL12_CK_DIV1 165
|
||||
#define CLK_TOP_APLL12_CK_DIV2 166
|
||||
#define CLK_TOP_APLL12_CK_DIV3 167
|
||||
#define CLK_TOP_APLL12_CK_DIV4 168
|
||||
#define CLK_TOP_APLL12_CK_DIV4B 169
|
||||
#define CLK_TOP_APLL12_CK_DIV5 170
|
||||
#define CLK_TOP_APLL12_CK_DIV5B 171
|
||||
#define CLK_TOP_APLL12_CK_DIV6 172
|
||||
#define CLK_TOP_USB_78M 173
|
||||
#define CLK_TOP_MSDC0_INFRA 174
|
||||
#define CLK_TOP_MSDC1_INFRA 175
|
||||
#define CLK_TOP_MSDC2_INFRA 176
|
||||
#define CLK_TOP_NR_CLK 177
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT8516_H */
|
||||
@@ -146,6 +146,10 @@
|
||||
#define GCC_MDP_TBU_CLK 138
|
||||
#define GCC_QDSS_DAP_CLK 139
|
||||
#define GCC_DCC_XO_CLK 140
|
||||
#define GCC_CDSP_CFG_AHB_CLK 143
|
||||
#define GCC_BIMC_CDSP_CLK 144
|
||||
#define GCC_CDSP_TBU_CLK 145
|
||||
#define GCC_CDSP_BIMC_CLK_SRC 146
|
||||
|
||||
#define GCC_GENI_IR_BCR 0
|
||||
#define GCC_USB_HS_BCR 1
|
||||
@@ -161,5 +165,6 @@
|
||||
#define GCC_PCIE_0_LINK_DOWN_BCR 11
|
||||
#define GCC_PCIEPHY_0_PHY_BCR 12
|
||||
#define GCC_EMAC_BCR 13
|
||||
#define GCC_CDSP_RESTART 14
|
||||
|
||||
#endif
|
||||
|
||||
15
include/dt-bindings/clock/qcom,turingcc-qcs404.h
Normal file
15
include/dt-bindings/clock/qcom,turingcc-qcs404.h
Normal file
@@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2019, Linaro Ltd
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H
|
||||
#define _DT_BINDINGS_CLK_TURING_QCS404_H
|
||||
|
||||
#define TURING_Q6SS_Q6_AXIM_CLK 0
|
||||
#define TURING_Q6SS_AHBM_AON_CLK 1
|
||||
#define TURING_WRAPPER_AON_CLK 2
|
||||
#define TURING_Q6SS_AHBS_AON_CLK 3
|
||||
#define TURING_WRAPPER_QOS_AHBS_AON_CLK 4
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user