rt2x00:Add VCO recalibration
Signed-off-by: John Li <chen-yang.li@mediatek.com> Acked-by: Gertjan van Wingerde <gwingerde@gmail.com> Acked-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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committed by
John W. Linville

parent
9da2723206
commit
2e9c43dd45
@@ -965,6 +965,7 @@
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* TX_PIN_CFG:
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*/
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#define TX_PIN_CFG 0x1328
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#define TX_PIN_CFG_PA_PE_DISABLE 0xfcfffff0
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#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
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#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
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#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
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@@ -985,6 +986,14 @@
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#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
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#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
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#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
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#define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
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#define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
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#define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
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#define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000)
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#define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000)
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#define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000)
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#define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000)
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#define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000)
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/*
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* TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
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