drm/tegra: Support DMA API for display controllers
If a display controller is not attached to an explicit IOMMU domain, which usually means that it's connected to an IOMMU domain controlled by the DMA API, make sure to map the framebuffer to the display controller address space. This allows us to transparently handle setups where the display controller is attached to an IOMMU or setups where it isn't. It also allows the driver to work with a DMA API that is backed by an IOMMU. Signed-off-by: Thierry Reding <treding@nvidia.com>
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@@ -413,7 +413,6 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
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unsigned int zpos = plane->state->normalized_zpos;
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struct drm_framebuffer *fb = plane->state->fb;
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struct tegra_plane *p = to_tegra_plane(plane);
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struct tegra_bo *bo;
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dma_addr_t base;
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u32 value;
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@@ -456,8 +455,7 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
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/* disable compression */
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tegra_plane_writel(p, 0, DC_WINBUF_CDE_CONTROL);
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bo = tegra_fb_get_plane(fb, 0);
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base = bo->iova;
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base = state->iova[0] + fb->offsets[0];
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tegra_plane_writel(p, state->format, DC_WIN_COLOR_DEPTH);
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tegra_plane_writel(p, 0, DC_WIN_PRECOMP_WGRP_PARAMS);
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@@ -521,6 +519,8 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
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}
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static const struct drm_plane_helper_funcs tegra_shared_plane_helper_funcs = {
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.prepare_fb = tegra_plane_prepare_fb,
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.cleanup_fb = tegra_plane_cleanup_fb,
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.atomic_check = tegra_shared_plane_atomic_check,
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.atomic_update = tegra_shared_plane_atomic_update,
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.atomic_disable = tegra_shared_plane_atomic_disable,
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