Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms. A bulk of this is smaller fixes or cleanups, but some of the new material this time around is: - Support for Nvidia Tegra234 SoC - Ring accelerator support for TI AM65x - PRUSS driver for TI platforms - Renesas support for R-Car V3U SoC - Reset support for Cortex-M4 processor on i.MX8MQ There are also new socinfo entries for a handful of different SoCs and platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (131 commits) drm/mediatek: reduce clear event soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api soc: mediatek: cmdq: add jump function soc: mediatek: cmdq: add write_s_mask value function soc: mediatek: cmdq: add write_s value function soc: mediatek: cmdq: add read_s function soc: mediatek: cmdq: add write_s_mask function soc: mediatek: cmdq: add write_s function soc: mediatek: cmdq: add address shift in jump soc: mediatek: mtk-infracfg: Fix kerneldoc soc: amlogic: pm-domains: use always-on flag reset: sti: reset-syscfg: fix struct description warnings reset: imx7: add the cm4 reset for i.MX8MQ dt-bindings: reset: imx8mq: add m4 reset reset: Fix and extend kerneldoc reset: reset-zynqmp: Added support for Versal platform dt-bindings: reset: Updated binding for Versal reset driver reset: imx7: Support module build soc: fsl: qe: Remove unnessesary check in ucc_set_tdm_rxtx_clk soc: fsl: qman: convert to use be32_add_cpu() ...
This commit is contained in:
Linus Torvalds
@@ -10,7 +10,8 @@ Required properties:
|
||||
"brcm,bcm7038-gisb-arb" for 130nm chips
|
||||
- reg: specifies the base physical address and size of the registers
|
||||
- interrupts: specifies the two interrupts (timeout and TEA) to be used from
|
||||
the parent interrupt controller
|
||||
the parent interrupt controller. A third optional interrupt may be specified
|
||||
for breakpoints.
|
||||
|
||||
Optional properties:
|
||||
|
||||
|
||||
@@ -5,7 +5,7 @@ The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
|
||||
Mediatek SMI have two generations of HW architecture, here is the list
|
||||
which generation the SoCs use:
|
||||
generation 1: mt2701 and mt7623.
|
||||
generation 2: mt2712, mt6779, mt8173 and mt8183.
|
||||
generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
|
||||
|
||||
There's slight differences between the two SMI, for generation 2, the
|
||||
register which control the iommu port is at each larb's register base. But
|
||||
@@ -20,6 +20,7 @@ Required properties:
|
||||
"mediatek,mt2712-smi-common"
|
||||
"mediatek,mt6779-smi-common"
|
||||
"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
|
||||
"mediatek,mt8167-smi-common"
|
||||
"mediatek,mt8173-smi-common"
|
||||
"mediatek,mt8183-smi-common"
|
||||
- reg : the register and size of the SMI block.
|
||||
|
||||
@@ -8,6 +8,7 @@ Required properties:
|
||||
"mediatek,mt2712-smi-larb"
|
||||
"mediatek,mt6779-smi-larb"
|
||||
"mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"
|
||||
"mediatek,mt8167-smi-larb"
|
||||
"mediatek,mt8173-smi-larb"
|
||||
"mediatek,mt8183-smi-larb"
|
||||
- reg : the register and size of this local arbiter.
|
||||
@@ -22,7 +23,7 @@ Required properties:
|
||||
- "gals": the clock for GALS(Global Async Local Sync).
|
||||
Here is the list which has this GALS: mt8183.
|
||||
|
||||
Required property for mt2701, mt2712, mt6779 and mt7623:
|
||||
Required property for mt2701, mt2712, mt6779, mt7623 and mt8167:
|
||||
- mediatek,larb-id :the hardware id of this larb.
|
||||
|
||||
Example:
|
||||
|
||||
@@ -27,6 +27,7 @@ properties:
|
||||
- amlogic,meson8b-pwrc
|
||||
- amlogic,meson8m2-pwrc
|
||||
- amlogic,meson-gxbb-pwrc
|
||||
- amlogic,meson-axg-pwrc
|
||||
- amlogic,meson-g12a-pwrc
|
||||
- amlogic,meson-sm1-pwrc
|
||||
|
||||
@@ -42,11 +43,11 @@ properties:
|
||||
- const: vapb
|
||||
|
||||
resets:
|
||||
minItems: 11
|
||||
minItems: 5
|
||||
maxItems: 12
|
||||
|
||||
reset-names:
|
||||
minItems: 11
|
||||
minItems: 5
|
||||
maxItems: 12
|
||||
|
||||
"#power-domain-cells":
|
||||
@@ -107,6 +108,24 @@ allOf:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,meson-axg-pwrc
|
||||
then:
|
||||
properties:
|
||||
reset-names:
|
||||
items:
|
||||
- const: viu
|
||||
- const: venc
|
||||
- const: vcbus
|
||||
- const: vencl
|
||||
- const: vid_lock
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -0,0 +1,44 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/power/brcm,bcm63xx-power.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: BCM63xx power domain driver
|
||||
|
||||
maintainers:
|
||||
- Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
|
||||
description: |
|
||||
BCM6318, BCM6328, BCM6362 and BCM63268 SoCs have a power domain controller
|
||||
to enable/disable certain components in order to save power.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm6318-power-controller
|
||||
- brcm,bcm6328-power-controller
|
||||
- brcm,bcm6362-power-controller
|
||||
- brcm,bcm63268-power-controller
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#power-domain-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#power-domain-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
periph_pwr: power-controller@10001848 {
|
||||
compatible = "brcm,bcm6328-power-controller";
|
||||
reg = <0x10001848 0x4>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
@@ -1,7 +1,7 @@
|
||||
--------------------------------------------------------------------------
|
||||
= Zynq UltraScale+ MPSoC reset driver binding =
|
||||
= Zynq UltraScale+ MPSoC and Versal reset driver binding =
|
||||
--------------------------------------------------------------------------
|
||||
The Zynq UltraScale+ MPSoC has several different resets.
|
||||
The Zynq UltraScale+ MPSoC and Versal has several different resets.
|
||||
|
||||
See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
|
||||
about zynqmp resets.
|
||||
@@ -10,7 +10,8 @@ Please also refer to reset.txt in this directory for common reset
|
||||
controller binding usage.
|
||||
|
||||
Required Properties:
|
||||
- compatible: "xlnx,zynqmp-reset"
|
||||
- compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
|
||||
"xlnx,versal-reset" for Versal platform
|
||||
- #reset-cells: Specifies the number of cells needed to encode reset
|
||||
line, should be 1
|
||||
|
||||
@@ -37,8 +38,10 @@ Device nodes that need access to reset lines should
|
||||
specify them as a reset phandle in their corresponding node as
|
||||
specified in reset.txt.
|
||||
|
||||
For list of all valid reset indicies see
|
||||
For list of all valid reset indices for Zynq UltraScale+ MPSoC see
|
||||
<dt-bindings/reset/xlnx-zynqmp-resets.h>
|
||||
For list of all valid reset indices for Versal see
|
||||
<dt-bindings/reset/xlnx-versal-resets.h>
|
||||
|
||||
Example:
|
||||
|
||||
|
||||
@@ -62,11 +62,6 @@ properties:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: TI-SCI device id of the ring accelerator
|
||||
|
||||
ti,dma-ring-reset-quirk:
|
||||
$ref: /schemas/types.yaml#definitions/flag
|
||||
description: |
|
||||
enable ringacc/udma ring state interoperability issue software w/a
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@@ -94,7 +89,6 @@ examples:
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <818>;
|
||||
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
|
||||
ti,dma-ring-reset-quirk;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <187>;
|
||||
msi-parent = <&inta_main_udmass>;
|
||||
|
||||
439
Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
Normal file
439
Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
Normal file
@@ -0,0 +1,439 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: |+
|
||||
TI Programmable Real-Time Unit and Industrial Communication Subsystem
|
||||
|
||||
maintainers:
|
||||
- Suman Anna <s-anna@ti.com>
|
||||
|
||||
description: |+
|
||||
|
||||
The Programmable Real-Time Unit and Industrial Communication Subsystem
|
||||
(PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
|
||||
Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
|
||||
cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
|
||||
instruction RAMs, some internal peripheral modules to facilitate industrial
|
||||
communication, and an interrupt controller.
|
||||
|
||||
The programmable nature of the PRUs provide flexibility to implement custom
|
||||
peripheral interfaces, fast real-time responses, or specialized data handling.
|
||||
The common peripheral modules include the following,
|
||||
- an Ethernet MII_RT module with two MII ports
|
||||
- an MDIO port to control external Ethernet PHYs
|
||||
- an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial
|
||||
Ethernet functions
|
||||
- an Enhanced Capture Module (eCAP)
|
||||
- an Industrial Ethernet Timer with 7/9 capture and 16 compare events
|
||||
- a 16550-compatible UART to support PROFIBUS
|
||||
- Enhanced GPIO with async capture and serial support
|
||||
|
||||
A PRU-ICSS subsystem can have up to three shared data memories. A PRU core
|
||||
acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
|
||||
0x0, but also has access to a secondary Data RAM (primary to the other PRU
|
||||
core) at its address 0x2000. A shared Data RAM, if present, can be accessed
|
||||
by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are
|
||||
common to both the PRU cores. Each PRU core also has a private instruction
|
||||
RAM, and specific register spaces for Control and Debug functionalities.
|
||||
|
||||
Various sub-modules within a PRU-ICSS subsystem are represented as individual
|
||||
nodes and are defined using a parent-child hierarchy depending on their
|
||||
integration within the IP and the SoC. These nodes are described in the
|
||||
following sections.
|
||||
|
||||
|
||||
PRU-ICSS Node
|
||||
==============
|
||||
Each PRU-ICSS instance is represented as its own node with the individual PRU
|
||||
processor cores, the memories node, an INTC node and an MDIO node represented
|
||||
as child nodes within this PRUSS node. This node shall be a child of the
|
||||
corresponding interconnect bus nodes or target-module nodes.
|
||||
|
||||
See ../../mfd/syscon.yaml for generic SysCon binding details.
|
||||
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^(pruss|icssg)@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- ti,am3356-pruss # for AM335x SoC family
|
||||
- ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
|
||||
- ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1
|
||||
- ti,am5728-pruss # for AM57xx SoC family
|
||||
- ti,k2g-pruss # for 66AK2G SoC family
|
||||
- ti,am654-icssg # for K3 AM65x SoC family
|
||||
- ti,j721e-icssg # for K3 J721E SoC family
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
ranges:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description: |
|
||||
This property is as per sci-pm-domain.txt.
|
||||
|
||||
patternProperties:
|
||||
|
||||
memories@[a-f0-9]+$:
|
||||
description: |
|
||||
The various Data RAMs within a single PRU-ICSS unit are represented as a
|
||||
single node with the name 'memories'.
|
||||
|
||||
type: object
|
||||
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM.
|
||||
maxItems: 3
|
||||
items:
|
||||
- description: Address and size of the Data RAM0.
|
||||
- description: Address and size of the Data RAM1.
|
||||
- description: |
|
||||
Address and size of the Shared Data RAM. Note that on AM437x one
|
||||
of two PRUSS units don't contain Shared RAM, while the second one
|
||||
has it.
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
items:
|
||||
- const: dram0
|
||||
- const: dram1
|
||||
- const: shrdram2
|
||||
|
||||
required:
|
||||
- reg
|
||||
- reg-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
cfg@[a-f0-9]+$:
|
||||
description: |
|
||||
PRU-ICSS configuration space. CFG sub-module represented as a SysCon.
|
||||
|
||||
type: object
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: ti,pruss-cfg
|
||||
- const: syscon
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ranges:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
type: object
|
||||
|
||||
properties:
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
coreclk-mux@[a-f0-9]+$:
|
||||
description: |
|
||||
This is applicable only for ICSSG (K3 SoCs). The ICSSG modules
|
||||
core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or
|
||||
ICSSG_ICLK. This node models this clock mux and should have the
|
||||
name "coreclk-mux".
|
||||
|
||||
type: object
|
||||
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: ICSSG_CORE Clock
|
||||
- description: ICSSG_ICLK Clock
|
||||
|
||||
assigned-clocks:
|
||||
maxItems: 1
|
||||
|
||||
assigned-clock-parents:
|
||||
maxItems: 1
|
||||
description: |
|
||||
Standard assigned-clocks-parents definition used for selecting
|
||||
mux parent (one of the mux input).
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
iepclk-mux@[a-f0-9]+$:
|
||||
description: |
|
||||
The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or
|
||||
CORE_CLK (OCP_CLK in older SoCs). This node models this clock
|
||||
mux and should have the name "iepclk-mux".
|
||||
|
||||
type: object
|
||||
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: ICSSG_IEP Clock
|
||||
- description: Core Clock (OCP Clock in older SoCs)
|
||||
|
||||
assigned-clocks:
|
||||
maxItems: 1
|
||||
|
||||
assigned-clock-parents:
|
||||
maxItems: 1
|
||||
description: |
|
||||
Standard assigned-clocks-parents definition used for selecting
|
||||
mux parent (one of the mux input).
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
iep@[a-f0-9]+$:
|
||||
description: |
|
||||
Industrial Ethernet Peripheral to manage/generate Industrial Ethernet
|
||||
functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x,
|
||||
AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x & J721E SoCs ). IEP
|
||||
is used for creating PTP clocks and generating PPS signals.
|
||||
|
||||
type: object
|
||||
|
||||
mii-rt@[a-f0-9]+$:
|
||||
description: |
|
||||
Real-Time Ethernet to support multiple industrial communication protocols.
|
||||
MII-RT sub-module represented as a SysCon.
|
||||
|
||||
type: object
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: ti,pruss-mii
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
mii-g-rt@[a-f0-9]+$:
|
||||
description: |
|
||||
The Real-time Media Independent Interface to support multiple industrial
|
||||
communication protocols (G stands for Gigabit). MII-G-RT sub-module
|
||||
represented as a SysCon.
|
||||
|
||||
type: object
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: ti,pruss-mii-g
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
interrupt-controller@[a-f0-9]+$:
|
||||
description: |
|
||||
PRUSS INTC Node. Each PRUSS has a single interrupt controller instance
|
||||
that is common to all the PRU cores. This should be represented as an
|
||||
interrupt-controller node.
|
||||
|
||||
type: object
|
||||
|
||||
mdio@[a-f0-9]+$:
|
||||
description: |
|
||||
MDIO Node. Each PRUSS has an MDIO module that can be used to control
|
||||
external PHYs. The MDIO module used within the PRU-ICSS is an instance of
|
||||
the MDIO Controller used in TI Davinci SoCs.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/net/ti,davinci-mdio.yaml#
|
||||
|
||||
type: object
|
||||
|
||||
"^(pru|rtu|txpru)@[0-9a-f]+$":
|
||||
description: |
|
||||
PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc
|
||||
device through a PRU child node each. Each node can optionally be rendered
|
||||
inactive by using the standard DT string property, "status". The ICSSG IP
|
||||
present on K3 SoCs have additional auxiliary PRU cores with slightly
|
||||
different IP integration.
|
||||
|
||||
type: object
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
# Due to inability of correctly verifying sub-nodes with an @address through
|
||||
# the "required" list, the required sub-nodes below are commented out for now.
|
||||
|
||||
#required:
|
||||
# - memories
|
||||
# - interrupt-controller
|
||||
# - pru
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- ti,k2g-pruss
|
||||
- ti,am654-icssg
|
||||
- ti,j721e-icssg
|
||||
then:
|
||||
required:
|
||||
- power-domains
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
/* Example 1 AM33xx PRU-ICSS */
|
||||
pruss: pruss@0 {
|
||||
compatible = "ti,am3356-pruss";
|
||||
reg = <0x0 0x80000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pruss_mem: memories@0 {
|
||||
reg = <0x0 0x2000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x10000 0x3000>;
|
||||
reg-names = "dram0", "dram1", "shrdram2";
|
||||
};
|
||||
|
||||
pruss_cfg: cfg@26000 {
|
||||
compatible = "ti,pruss-cfg", "syscon";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x26000 0x2000>;
|
||||
ranges = <0x00 0x26000 0x2000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pruss_iepclk_mux: iepclk-mux@30 {
|
||||
reg = <0x30>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&l3_gclk>, /* icss_iep */
|
||||
<&pruss_ocp_gclk>; /* icss_ocp */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pruss_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x58>;
|
||||
};
|
||||
|
||||
pruss_mdio: mdio@32400 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
reg = <0x32400 0x90>;
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
|
||||
/* Example 2 AM43xx PRU-ICSS with PRUSS1 node */
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
pruss1: pruss@0 {
|
||||
compatible = "ti,am4376-pruss1";
|
||||
reg = <0x0 0x40000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pruss1_mem: memories@0 {
|
||||
reg = <0x0 0x2000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x10000 0x8000>;
|
||||
reg-names = "dram0", "dram1", "shrdram2";
|
||||
};
|
||||
|
||||
pruss1_cfg: cfg@26000 {
|
||||
compatible = "ti,pruss-cfg", "syscon";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x26000 0x2000>;
|
||||
ranges = <0x00 0x26000 0x2000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pruss1_iepclk_mux: iepclk-mux@30 {
|
||||
reg = <0x30>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&sysclk_div>, /* icss_iep */
|
||||
<&pruss_ocp_gclk>; /* icss_ocp */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pruss1_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x58>;
|
||||
};
|
||||
|
||||
pruss1_mdio: mdio@32400 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
reg = <0x32400 0x90>;
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
Reference in New Issue
Block a user