arm64: Emulate SETEND for AArch32 tasks
Emulate deprecated 'setend' instruction for AArch32 bit tasks. setend [le/be] - Sets the endianness of EL0 On systems with CPUs which support mixed endian at EL0, the hardware support for the instruction can be enabled by setting the SCTLR_EL1.SED bit. Like the other emulated instructions it is controlled by an entry in /proc/sys/abi/. For more information see : Documentation/arm64/legacy_instructions.txt The instruction is emulated by setting/clearing the SPSR_EL1.E bit, which will be reflected in the PSTATE.E in AArch32 context. This patch also restores the native endianness for the execution of signal handlers, since the process could have changed the endianness. Note: All CPUs on the system must have mixed endian support at EL0. Once the handler is registered, hotplugging a CPU which doesn't support mixed endian, could lead to unexpected results/behavior in applications. Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas

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@@ -32,6 +32,9 @@ The default mode depends on the status of the instruction in the
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architecture. Deprecated instructions should default to emulation
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while obsolete instructions must be undefined by default.
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Note: Instruction emulation may not be possible in all cases. See
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individual instruction notes for further information.
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Supported legacy instructions
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-----------------------------
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* SWP{B}
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@@ -43,3 +46,12 @@ Default: Undef (0)
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Node: /proc/sys/abi/cp15_barrier
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Status: Deprecated
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Default: Emulate (1)
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* SETEND
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Node: /proc/sys/abi/setend
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Status: Deprecated
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Default: Emulate (1)*
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Note: All the cpus on the system must have mixed endian support at EL0
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for this feature to be enabled. If a new CPU - which doesn't support mixed
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endian - is hotplugged in after this feature has been enabled, there could
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be unexpected results in the application.
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