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@@ -110,17 +110,18 @@ Type: system ioctl
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Parameters: machine type identifier (KVM_VM_*)
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Returns: a VM fd that can be used to control the new virtual machine.
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The new VM has no virtual cpus and no memory. An mmap() of a VM fd
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will access the virtual machine's physical address space; offset zero
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corresponds to guest physical address zero. Use of mmap() on a VM fd
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is discouraged if userspace memory allocation (KVM_CAP_USER_MEMORY) is
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available.
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You most certainly want to use 0 as machine type.
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The new VM has no virtual cpus and no memory.
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You probably want to use 0 as machine type.
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In order to create user controlled virtual machines on S390, check
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KVM_CAP_S390_UCONTROL and use the flag KVM_VM_S390_UCONTROL as
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privileged user (CAP_SYS_ADMIN).
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To use hardware assisted virtualization on MIPS (VZ ASE) rather than
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the default trap & emulate implementation (which changes the virtual
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memory layout to fit in user mode), check KVM_CAP_MIPS_VZ and use the
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flag KVM_VM_MIPS_VZ.
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4.3 KVM_GET_MSR_INDEX_LIST
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@@ -1321,130 +1322,6 @@ The flags bitmap is defined as:
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/* the host supports the ePAPR idle hcall
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#define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0)
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4.48 KVM_ASSIGN_PCI_DEVICE (deprecated)
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Capability: none
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Architectures: x86
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Type: vm ioctl
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Parameters: struct kvm_assigned_pci_dev (in)
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Returns: 0 on success, -1 on error
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Assigns a host PCI device to the VM.
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struct kvm_assigned_pci_dev {
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__u32 assigned_dev_id;
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__u32 busnr;
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__u32 devfn;
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__u32 flags;
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__u32 segnr;
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union {
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__u32 reserved[11];
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};
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};
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The PCI device is specified by the triple segnr, busnr, and devfn.
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Identification in succeeding service requests is done via assigned_dev_id. The
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following flags are specified:
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/* Depends on KVM_CAP_IOMMU */
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#define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0)
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/* The following two depend on KVM_CAP_PCI_2_3 */
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#define KVM_DEV_ASSIGN_PCI_2_3 (1 << 1)
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#define KVM_DEV_ASSIGN_MASK_INTX (1 << 2)
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If KVM_DEV_ASSIGN_PCI_2_3 is set, the kernel will manage legacy INTx interrupts
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via the PCI-2.3-compliant device-level mask, thus enable IRQ sharing with other
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assigned devices or host devices. KVM_DEV_ASSIGN_MASK_INTX specifies the
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guest's view on the INTx mask, see KVM_ASSIGN_SET_INTX_MASK for details.
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The KVM_DEV_ASSIGN_ENABLE_IOMMU flag is a mandatory option to ensure
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isolation of the device. Usages not specifying this flag are deprecated.
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Only PCI header type 0 devices with PCI BAR resources are supported by
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device assignment. The user requesting this ioctl must have read/write
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access to the PCI sysfs resource files associated with the device.
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Errors:
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ENOTTY: kernel does not support this ioctl
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Other error conditions may be defined by individual device types or
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have their standard meanings.
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4.49 KVM_DEASSIGN_PCI_DEVICE (deprecated)
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Capability: none
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Architectures: x86
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Type: vm ioctl
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Parameters: struct kvm_assigned_pci_dev (in)
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Returns: 0 on success, -1 on error
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Ends PCI device assignment, releasing all associated resources.
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See KVM_ASSIGN_PCI_DEVICE for the data structure. Only assigned_dev_id is
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used in kvm_assigned_pci_dev to identify the device.
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Errors:
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ENOTTY: kernel does not support this ioctl
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Other error conditions may be defined by individual device types or
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have their standard meanings.
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4.50 KVM_ASSIGN_DEV_IRQ (deprecated)
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Capability: KVM_CAP_ASSIGN_DEV_IRQ
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Architectures: x86
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Type: vm ioctl
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Parameters: struct kvm_assigned_irq (in)
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Returns: 0 on success, -1 on error
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Assigns an IRQ to a passed-through device.
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struct kvm_assigned_irq {
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__u32 assigned_dev_id;
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__u32 host_irq; /* ignored (legacy field) */
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__u32 guest_irq;
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__u32 flags;
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union {
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__u32 reserved[12];
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};
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};
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The following flags are defined:
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#define KVM_DEV_IRQ_HOST_INTX (1 << 0)
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#define KVM_DEV_IRQ_HOST_MSI (1 << 1)
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#define KVM_DEV_IRQ_HOST_MSIX (1 << 2)
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#define KVM_DEV_IRQ_GUEST_INTX (1 << 8)
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#define KVM_DEV_IRQ_GUEST_MSI (1 << 9)
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#define KVM_DEV_IRQ_GUEST_MSIX (1 << 10)
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It is not valid to specify multiple types per host or guest IRQ. However, the
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IRQ type of host and guest can differ or can even be null.
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Errors:
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ENOTTY: kernel does not support this ioctl
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Other error conditions may be defined by individual device types or
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have their standard meanings.
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4.51 KVM_DEASSIGN_DEV_IRQ (deprecated)
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Capability: KVM_CAP_ASSIGN_DEV_IRQ
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Architectures: x86
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Type: vm ioctl
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Parameters: struct kvm_assigned_irq (in)
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Returns: 0 on success, -1 on error
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Ends an IRQ assignment to a passed-through device.
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See KVM_ASSIGN_DEV_IRQ for the data structure. The target device is specified
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by assigned_dev_id, flags must correspond to the IRQ type specified on
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KVM_ASSIGN_DEV_IRQ. Partial deassignment of host or guest IRQ is allowed.
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4.52 KVM_SET_GSI_ROUTING
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Capability: KVM_CAP_IRQ_ROUTING
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@@ -1531,52 +1408,6 @@ struct kvm_irq_routing_hv_sint {
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__u32 sint;
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};
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4.53 KVM_ASSIGN_SET_MSIX_NR (deprecated)
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Capability: none
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Architectures: x86
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Type: vm ioctl
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Parameters: struct kvm_assigned_msix_nr (in)
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Returns: 0 on success, -1 on error
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Set the number of MSI-X interrupts for an assigned device. The number is
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reset again by terminating the MSI-X assignment of the device via
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KVM_DEASSIGN_DEV_IRQ. Calling this service more than once at any earlier
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point will fail.
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struct kvm_assigned_msix_nr {
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__u32 assigned_dev_id;
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__u16 entry_nr;
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__u16 padding;
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};
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#define KVM_MAX_MSIX_PER_DEV 256
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4.54 KVM_ASSIGN_SET_MSIX_ENTRY (deprecated)
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Capability: none
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Architectures: x86
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Type: vm ioctl
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Parameters: struct kvm_assigned_msix_entry (in)
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Returns: 0 on success, -1 on error
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Specifies the routing of an MSI-X assigned device interrupt to a GSI. Setting
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the GSI vector to zero means disabling the interrupt.
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struct kvm_assigned_msix_entry {
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__u32 assigned_dev_id;
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__u32 gsi;
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__u16 entry; /* The index of entry in the MSI-X table */
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__u16 padding[3];
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};
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Errors:
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ENOTTY: kernel does not support this ioctl
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Other error conditions may be defined by individual device types or
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have their standard meanings.
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4.55 KVM_SET_TSC_KHZ
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@@ -1728,40 +1559,6 @@ should skip processing the bitmap and just invalidate everything. It must
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be set to the number of set bits in the bitmap.
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4.61 KVM_ASSIGN_SET_INTX_MASK (deprecated)
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Capability: KVM_CAP_PCI_2_3
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Architectures: x86
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Type: vm ioctl
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Parameters: struct kvm_assigned_pci_dev (in)
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Returns: 0 on success, -1 on error
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Allows userspace to mask PCI INTx interrupts from the assigned device. The
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kernel will not deliver INTx interrupts to the guest between setting and
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clearing of KVM_ASSIGN_SET_INTX_MASK via this interface. This enables use of
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and emulation of PCI 2.3 INTx disable command register behavior.
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This may be used for both PCI 2.3 devices supporting INTx disable natively and
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older devices lacking this support. Userspace is responsible for emulating the
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read value of the INTx disable bit in the guest visible PCI command register.
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When modifying the INTx disable state, userspace should precede updating the
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physical device command register by calling this ioctl to inform the kernel of
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the new intended INTx mask state.
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Note that the kernel uses the device INTx disable bit to internally manage the
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device interrupt state for PCI 2.3 devices. Reads of this register may
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therefore not match the expected value. Writes should always use the guest
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intended INTx disable value rather than attempting to read-copy-update the
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current physical device state. Races between user and kernel updates to the
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INTx disable bit are handled lazily in the kernel. It's possible the device
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may generate unintended interrupts, but they will not be injected into the
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guest.
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See KVM_ASSIGN_DEV_IRQ for the data structure. The target device is specified
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by assigned_dev_id. In the flags field, only KVM_DEV_ASSIGN_MASK_INTX is
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evaluated.
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4.62 KVM_CREATE_SPAPR_TCE
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Capability: KVM_CAP_SPAPR_TCE
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@@ -2068,11 +1865,23 @@ registers, find a list below:
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MIPS | KVM_REG_MIPS_CP0_ENTRYLO0 | 64
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MIPS | KVM_REG_MIPS_CP0_ENTRYLO1 | 64
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MIPS | KVM_REG_MIPS_CP0_CONTEXT | 64
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MIPS | KVM_REG_MIPS_CP0_CONTEXTCONFIG| 32
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MIPS | KVM_REG_MIPS_CP0_USERLOCAL | 64
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MIPS | KVM_REG_MIPS_CP0_XCONTEXTCONFIG| 64
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MIPS | KVM_REG_MIPS_CP0_PAGEMASK | 32
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MIPS | KVM_REG_MIPS_CP0_PAGEGRAIN | 32
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MIPS | KVM_REG_MIPS_CP0_SEGCTL0 | 64
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MIPS | KVM_REG_MIPS_CP0_SEGCTL1 | 64
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MIPS | KVM_REG_MIPS_CP0_SEGCTL2 | 64
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MIPS | KVM_REG_MIPS_CP0_PWBASE | 64
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MIPS | KVM_REG_MIPS_CP0_PWFIELD | 64
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MIPS | KVM_REG_MIPS_CP0_PWSIZE | 64
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MIPS | KVM_REG_MIPS_CP0_WIRED | 32
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MIPS | KVM_REG_MIPS_CP0_PWCTL | 32
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MIPS | KVM_REG_MIPS_CP0_HWRENA | 32
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MIPS | KVM_REG_MIPS_CP0_BADVADDR | 64
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MIPS | KVM_REG_MIPS_CP0_BADINSTR | 32
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MIPS | KVM_REG_MIPS_CP0_BADINSTRP | 32
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MIPS | KVM_REG_MIPS_CP0_COUNT | 32
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MIPS | KVM_REG_MIPS_CP0_ENTRYHI | 64
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MIPS | KVM_REG_MIPS_CP0_COMPARE | 32
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@@ -2089,6 +1898,7 @@ registers, find a list below:
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MIPS | KVM_REG_MIPS_CP0_CONFIG4 | 32
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MIPS | KVM_REG_MIPS_CP0_CONFIG5 | 32
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MIPS | KVM_REG_MIPS_CP0_CONFIG7 | 32
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MIPS | KVM_REG_MIPS_CP0_XCONTEXT | 64
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MIPS | KVM_REG_MIPS_CP0_ERROREPC | 64
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MIPS | KVM_REG_MIPS_CP0_KSCRATCH1 | 64
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MIPS | KVM_REG_MIPS_CP0_KSCRATCH2 | 64
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@@ -2096,6 +1906,7 @@ registers, find a list below:
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MIPS | KVM_REG_MIPS_CP0_KSCRATCH4 | 64
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MIPS | KVM_REG_MIPS_CP0_KSCRATCH5 | 64
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MIPS | KVM_REG_MIPS_CP0_KSCRATCH6 | 64
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MIPS | KVM_REG_MIPS_CP0_MAAR(0..63) | 64
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MIPS | KVM_REG_MIPS_COUNT_CTL | 64
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MIPS | KVM_REG_MIPS_COUNT_RESUME | 64
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MIPS | KVM_REG_MIPS_COUNT_HZ | 64
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@@ -2162,6 +1973,10 @@ hardware, host kernel, guest, and whether XPA is present in the guest, i.e.
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with the RI and XI bits (if they exist) in bits 63 and 62 respectively, and
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the PFNX field starting at bit 30.
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MIPS MAARs (see KVM_REG_MIPS_CP0_MAAR(*) above) have the following id bit
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patterns:
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0x7030 0000 0001 01 <reg:8>
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MIPS KVM control registers (see above) have the following id bit patterns:
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0x7030 0000 0002 <reg:16>
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@@ -4164,6 +3979,23 @@ to take care of that.
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This capability can be enabled dynamically even if VCPUs were already
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created and are running.
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7.9 KVM_CAP_S390_GS
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Architectures: s390
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Parameters: none
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Returns: 0 on success; -EINVAL if the machine does not support
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guarded storage; -EBUSY if a VCPU has already been created.
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Allows use of guarded storage for the KVM guest.
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7.10 KVM_CAP_S390_AIS
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Architectures: s390
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Parameters: none
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Allow use of adapter-interruption suppression.
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Returns: 0 on success; -EBUSY if a VCPU has already been created.
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8. Other capabilities.
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----------------------
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@@ -4210,3 +4042,118 @@ This capability, if KVM_CHECK_EXTENSION indicates that it is
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available, means that that the kernel can support guests using the
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hashed page table MMU defined in Power ISA V3.00 (as implemented in
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the POWER9 processor), including in-memory segment tables.
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8.5 KVM_CAP_MIPS_VZ
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Architectures: mips
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This capability, if KVM_CHECK_EXTENSION on the main kvm handle indicates that
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it is available, means that full hardware assisted virtualization capabilities
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of the hardware are available for use through KVM. An appropriate
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KVM_VM_MIPS_* type must be passed to KVM_CREATE_VM to create a VM which
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utilises it.
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If KVM_CHECK_EXTENSION on a kvm VM handle indicates that this capability is
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available, it means that the VM is using full hardware assisted virtualization
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capabilities of the hardware. This is useful to check after creating a VM with
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KVM_VM_MIPS_DEFAULT.
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The value returned by KVM_CHECK_EXTENSION should be compared against known
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values (see below). All other values are reserved. This is to allow for the
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possibility of other hardware assisted virtualization implementations which
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may be incompatible with the MIPS VZ ASE.
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0: The trap & emulate implementation is in use to run guest code in user
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mode. Guest virtual memory segments are rearranged to fit the guest in the
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user mode address space.
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1: The MIPS VZ ASE is in use, providing full hardware assisted
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virtualization, including standard guest virtual memory segments.
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8.6 KVM_CAP_MIPS_TE
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Architectures: mips
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This capability, if KVM_CHECK_EXTENSION on the main kvm handle indicates that
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it is available, means that the trap & emulate implementation is available to
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run guest code in user mode, even if KVM_CAP_MIPS_VZ indicates that hardware
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assisted virtualisation is also available. KVM_VM_MIPS_TE (0) must be passed
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to KVM_CREATE_VM to create a VM which utilises it.
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If KVM_CHECK_EXTENSION on a kvm VM handle indicates that this capability is
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available, it means that the VM is using trap & emulate.
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8.7 KVM_CAP_MIPS_64BIT
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Architectures: mips
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This capability indicates the supported architecture type of the guest, i.e. the
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supported register and address width.
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The values returned when this capability is checked by KVM_CHECK_EXTENSION on a
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kvm VM handle correspond roughly to the CP0_Config.AT register field, and should
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be checked specifically against known values (see below). All other values are
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reserved.
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0: MIPS32 or microMIPS32.
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Both registers and addresses are 32-bits wide.
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It will only be possible to run 32-bit guest code.
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1: MIPS64 or microMIPS64 with access only to 32-bit compatibility segments.
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Registers are 64-bits wide, but addresses are 32-bits wide.
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64-bit guest code may run but cannot access MIPS64 memory segments.
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It will also be possible to run 32-bit guest code.
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2: MIPS64 or microMIPS64 with access to all address segments.
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Both registers and addresses are 64-bits wide.
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It will be possible to run 64-bit or 32-bit guest code.
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8.8 KVM_CAP_X86_GUEST_MWAIT
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Architectures: x86
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This capability indicates that guest using memory monotoring instructions
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(MWAIT/MWAITX) to stop the virtual CPU will not cause a VM exit. As such time
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spent while virtual CPU is halted in this way will then be accounted for as
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guest running time on the host (as opposed to e.g. HLT).
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8.9 KVM_CAP_ARM_USER_IRQ
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Architectures: arm, arm64
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This capability, if KVM_CHECK_EXTENSION indicates that it is available, means
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that if userspace creates a VM without an in-kernel interrupt controller, it
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will be notified of changes to the output level of in-kernel emulated devices,
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which can generate virtual interrupts, presented to the VM.
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For such VMs, on every return to userspace, the kernel
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updates the vcpu's run->s.regs.device_irq_level field to represent the actual
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output level of the device.
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Whenever kvm detects a change in the device output level, kvm guarantees at
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least one return to userspace before running the VM. This exit could either
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be a KVM_EXIT_INTR or any other exit event, like KVM_EXIT_MMIO. This way,
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userspace can always sample the device output level and re-compute the state of
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the userspace interrupt controller. Userspace should always check the state
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of run->s.regs.device_irq_level on every kvm exit.
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The value in run->s.regs.device_irq_level can represent both level and edge
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triggered interrupt signals, depending on the device. Edge triggered interrupt
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signals will exit to userspace with the bit in run->s.regs.device_irq_level
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set exactly once per edge signal.
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The field run->s.regs.device_irq_level is available independent of
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run->kvm_valid_regs or run->kvm_dirty_regs bits.
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If KVM_CAP_ARM_USER_IRQ is supported, the KVM_CHECK_EXTENSION ioctl returns a
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number larger than 0 indicating the version of this capability is implemented
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and thereby which bits in in run->s.regs.device_irq_level can signal values.
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Currently the following bits are defined for the device_irq_level bitmap:
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KVM_CAP_ARM_USER_IRQ >= 1:
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KVM_ARM_DEV_EL1_VTIMER - EL1 virtual timer
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KVM_ARM_DEV_EL1_PTIMER - EL1 physical timer
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KVM_ARM_DEV_PMU - ARM PMU overflow interrupt signal
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Future versions of kvm may implement additional events. These will get
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indicated by returning a higher number from KVM_CHECK_EXTENSION and will be
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listed above.
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