xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

xtensa: dispatch medium-priority interrupts

Browse Source 
Add support for dispatching medium-priority interrupts, that is,
interrupts of priority levels 2 to EXCM_LEVEL. IRQ handling may be
preempted by higher priority IRQ.

Signed-off-by: Marc Gauthier <marc@tensilica.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
This commit is contained in:
Marc Gauthier
2013-01-05 04:57:17 +04:00
committed by Chris Zankel
parent d0b73b488c
commit 2d1c645cc5
10 changed files with 261 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/xtensa/include/asm/atomic.h
View File

@@ -7,7 +7,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001 - 2005 Tensilica Inc.
* Copyright (C) 2001 - 2008 Tensilica Inc.
*/
#ifndef _XTENSA_ATOMIC_H
@@ -24,11 +24,11 @@
/*
* This Xtensa implementation assumes that the right mechanism
* for exclusion is for locking interrupts to level 1.
* for exclusion is for locking interrupts to level EXCM_LEVEL.
*
* Locking interrupts looks like this:
*
* rsil a15, 1
* rsil a15, LOCKLEVEL
* <code>
* wsr a15, PS
* rsync