drm/i915: Embedded struct drm_crtc_state in intel_crtc_state
And get rid of the duplicate mode structures. This patch was generated
with the following semantic patch:
@@ @@
struct intel_crtc_state {
+struct drm_crtc_state base;
+
...
-struct drm_display_mode requested_mode;
-struct drm_display_mode adjusted_mode;
...
}
@@ struct intel_crtc_state *state; @@
-state->adjusted_mode
+state->base.adjusted_mode
@@ struct intel_crtc_state *state; @@
-state->requested_mode
+state->base.mode
@@ struct intel_crtc_state state; @@
-state.adjusted_mode
+state.base.adjusted_mode
@@ struct intel_crtc_state state; @@
-state.requested_mode
+state.base.mode
@@ struct drm_crtc *crtc; @@
-to_intel_crtc(crtc)->config.adjusted_mode
+to_intel_crtc(crtc)->config.base.adjusted_mode
@@ identifier member; expression E; @@
-PIPE_CONF_CHECK_FLAGS(adjusted_mode.member, E);
+PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.member, E);
@@ identifier member; @@
-PIPE_CONF_CHECK_I(adjusted_mode.member);
+PIPE_CONF_CHECK_I(base.adjusted_mode.member);
@@ identifier member; @@
-PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.member);
+PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.member);
v2: Completely generate the patch with cocci. (Ander)
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ander Conselvan de Oliveira
committed by
Daniel Vetter
Daniel Vetter
parent
5cec258b4f
commit
2d112de7db
@@ -897,7 +897,7 @@ bool intel_crtc_active(struct drm_crtc *crtc)
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* properly reconstruct framebuffers.
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*/
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return intel_crtc->active && crtc->primary->fb &&
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intel_crtc->config.adjusted_mode.crtc_clock;
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intel_crtc->config.base.adjusted_mode.crtc_clock;
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}
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enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
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@@ -2941,7 +2941,7 @@ static void intel_update_pipe_size(struct intel_crtc *crtc)
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* then update the pipesrc and pfit state, even on the flip path.
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*/
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adjusted_mode = &crtc->config.adjusted_mode;
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adjusted_mode = &crtc->config.base.adjusted_mode;
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I915_WRITE(PIPESRC(crtc->pipe),
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((adjusted_mode->crtc_hdisplay - 1) << 16) |
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@@ -3577,7 +3577,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
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int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock;
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u32 divsel, phaseinc, auxdiv, phasedir = 0;
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u32 temp;
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@@ -4908,7 +4908,7 @@ static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
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for_each_intel_crtc(dev, intel_crtc) {
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if (intel_crtc->new_enabled)
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max_pixclk = max(max_pixclk,
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intel_crtc->new_config->adjusted_mode.crtc_clock);
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intel_crtc->new_config->base.adjusted_mode.crtc_clock);
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}
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return max_pixclk;
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@@ -5429,7 +5429,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
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struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
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int lane, link_bw, fdi_dotclock;
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bool setup_ok, needs_recompute = false;
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@@ -5484,7 +5484,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
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struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
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/* FIXME should check pixel clock limits on all platforms */
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if (INTEL_INFO(dev)->gen < 4) {
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@@ -6206,7 +6206,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
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enum pipe pipe = intel_crtc->pipe;
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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struct drm_display_mode *adjusted_mode =
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&intel_crtc->config.adjusted_mode;
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&intel_crtc->config.base.adjusted_mode;
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uint32_t crtc_vtotal, crtc_vblank_end;
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int vsyncshift = 0;
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@@ -6277,56 +6277,56 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
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uint32_t tmp;
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tmp = I915_READ(HTOTAL(cpu_transcoder));
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pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
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pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
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tmp = I915_READ(HBLANK(cpu_transcoder));
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pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
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pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
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tmp = I915_READ(HSYNC(cpu_transcoder));
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pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
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pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
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tmp = I915_READ(VTOTAL(cpu_transcoder));
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pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
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pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
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tmp = I915_READ(VBLANK(cpu_transcoder));
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pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
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pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
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tmp = I915_READ(VSYNC(cpu_transcoder));
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pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
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pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
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pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
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if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
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pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
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pipe_config->adjusted_mode.crtc_vtotal += 1;
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pipe_config->adjusted_mode.crtc_vblank_end += 1;
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pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
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pipe_config->base.adjusted_mode.crtc_vtotal += 1;
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pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
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}
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tmp = I915_READ(PIPESRC(crtc->pipe));
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pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
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pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
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pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
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pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
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pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
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pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
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}
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void intel_mode_from_pipe_config(struct drm_display_mode *mode,
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struct intel_crtc_state *pipe_config)
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{
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mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
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mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
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mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
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mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
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mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
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mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
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mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
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mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
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mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
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mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
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mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
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mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
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mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
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mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
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mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
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mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
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mode->flags = pipe_config->adjusted_mode.flags;
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mode->flags = pipe_config->base.adjusted_mode.flags;
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mode->clock = pipe_config->adjusted_mode.crtc_clock;
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mode->flags |= pipe_config->adjusted_mode.flags;
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mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
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mode->flags |= pipe_config->base.adjusted_mode.flags;
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}
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static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
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@@ -6376,7 +6376,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
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}
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}
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if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
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if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
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if (INTEL_INFO(dev)->gen < 4 ||
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intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
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pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
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@@ -7133,7 +7133,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
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if (intel_crtc->config.dither)
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val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
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if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
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if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
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val |= PIPECONF_INTERLACED_ILK;
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else
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val |= PIPECONF_PROGRESSIVE;
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@@ -7223,7 +7223,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
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if (IS_HASWELL(dev) && intel_crtc->config.dither)
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val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
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if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
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if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
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val |= PIPECONF_INTERLACED_ILK;
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else
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val |= PIPECONF_PROGRESSIVE;
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@@ -8789,7 +8789,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
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* agree once we know their relationship in the encoder's
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* get_config() function.
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*/
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pipe_config->adjusted_mode.crtc_clock =
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pipe_config->base.adjusted_mode.crtc_clock =
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intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
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&pipe_config->fdi_m_n);
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}
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@@ -9981,10 +9981,10 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
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pipe_config->has_infoframe);
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DRM_DEBUG_KMS("requested mode:\n");
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drm_mode_debug_printmodeline(&pipe_config->requested_mode);
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drm_mode_debug_printmodeline(&pipe_config->base.mode);
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DRM_DEBUG_KMS("adjusted mode:\n");
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drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
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intel_dump_crtc_timings(&pipe_config->adjusted_mode);
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drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
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intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
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DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
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DRM_DEBUG_KMS("pipe src size: %dx%d\n",
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pipe_config->pipe_src_w, pipe_config->pipe_src_h);
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@@ -10108,8 +10108,8 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
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if (!pipe_config)
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return ERR_PTR(-ENOMEM);
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drm_mode_copy(&pipe_config->adjusted_mode, mode);
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drm_mode_copy(&pipe_config->requested_mode, mode);
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drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
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drm_mode_copy(&pipe_config->base.mode, mode);
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pipe_config->cpu_transcoder =
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(enum transcoder) to_intel_crtc(crtc)->pipe;
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@@ -10120,13 +10120,13 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
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* positive or negative polarity is requested, treat this as meaning
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* negative polarity.
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*/
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if (!(pipe_config->adjusted_mode.flags &
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if (!(pipe_config->base.adjusted_mode.flags &
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(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
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pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
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pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
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if (!(pipe_config->adjusted_mode.flags &
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if (!(pipe_config->base.adjusted_mode.flags &
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(DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
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pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
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pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
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/* Compute a starting value for pipe_config->pipe_bpp taking the source
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* plane pixel format and any sink constraints into account. Returns the
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@@ -10145,7 +10145,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
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* computation to clearly distinguish it from the adjusted mode, which
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* can be changed by the connectors in the below retry loop.
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*/
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drm_crtc_get_hv_timing(&pipe_config->requested_mode,
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drm_crtc_get_hv_timing(&pipe_config->base.mode,
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&pipe_config->pipe_src_w,
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&pipe_config->pipe_src_h);
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@@ -10155,7 +10155,8 @@ encoder_retry:
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pipe_config->pixel_multiplier = 1;
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/* Fill in default crtc timings, allow encoders to overwrite them. */
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drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
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drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
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CRTC_STEREO_DOUBLE);
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/* Pass our mode to the connectors and the CRTC to give them a chance to
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* adjust it according to limitations or connector properties, and also
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@@ -10175,7 +10176,7 @@ encoder_retry:
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/* Set default port clock if not overwritten by the encoder. Needs to be
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* done afterwards in case the encoder adjusts the mode. */
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if (!pipe_config->port_clock)
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pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
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pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
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* pipe_config->pixel_multiplier;
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ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
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@@ -10476,19 +10477,19 @@ intel_pipe_config_compare(struct drm_device *dev,
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PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
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}
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PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
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PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
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PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
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PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
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PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
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PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
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PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
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PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
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PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
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PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
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PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
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PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
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PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
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PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
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PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
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PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
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PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
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PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
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PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
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PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
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PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
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PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
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PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
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PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
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PIPE_CONF_CHECK_I(pixel_multiplier);
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PIPE_CONF_CHECK_I(has_hdmi_sink);
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@@ -10499,17 +10500,17 @@ intel_pipe_config_compare(struct drm_device *dev,
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PIPE_CONF_CHECK_I(has_audio);
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PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
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PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
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DRM_MODE_FLAG_INTERLACE);
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if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
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PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
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PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
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DRM_MODE_FLAG_PHSYNC);
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PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
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PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
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DRM_MODE_FLAG_NHSYNC);
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PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
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PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
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DRM_MODE_FLAG_PVSYNC);
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PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
|
||||
PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
|
||||
DRM_MODE_FLAG_NVSYNC);
|
||||
}
|
||||
|
||||
@@ -10559,7 +10560,7 @@ intel_pipe_config_compare(struct drm_device *dev,
|
||||
if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
|
||||
PIPE_CONF_CHECK_I(pipe_bpp);
|
||||
|
||||
PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
|
||||
PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
|
||||
PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
|
||||
|
||||
#undef PIPE_CONF_CHECK_X
|
||||
@@ -10835,9 +10836,9 @@ void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
|
||||
* FDI already provided one idea for the dotclock.
|
||||
* Yell if the encoder disagrees.
|
||||
*/
|
||||
WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
|
||||
WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
|
||||
"FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
|
||||
pipe_config->adjusted_mode.crtc_clock, dotclock);
|
||||
pipe_config->base.adjusted_mode.crtc_clock, dotclock);
|
||||
}
|
||||
|
||||
static void update_scanline_offset(struct intel_crtc *crtc)
|
||||
@@ -10863,7 +10864,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
|
||||
* one to the value.
|
||||
*/
|
||||
if (IS_GEN2(dev)) {
|
||||
const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
|
||||
const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
|
||||
int vtotal;
|
||||
|
||||
vtotal = mode->crtc_vtotal;
|
||||
@@ -10992,7 +10993,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
|
||||
* timestamping. They are derived from true hwmode.
|
||||
*/
|
||||
drm_calc_timestamping_constants(crtc,
|
||||
&pipe_config->adjusted_mode);
|
||||
&pipe_config->base.adjusted_mode);
|
||||
}
|
||||
|
||||
/* Only after disabling all output pipelines that will be changed can we
|
||||
|
||||
Reference in New Issue
Block a user