igb: add 82576 MAC support
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
Alexander Duyck
committed by
Jeff Garzik
Jeff Garzik
parent
0024fd00cd
commit
2d064c06fe
@@ -827,8 +827,9 @@ err_setup:
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/* ethtool register test data */
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struct igb_reg_test {
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u16 reg;
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u8 array_len;
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u8 test_type;
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u16 reg_offset;
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u16 array_len;
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u16 test_type;
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u32 mask;
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u32 write;
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};
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@@ -850,34 +851,72 @@ struct igb_reg_test {
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#define TABLE64_TEST_LO 5
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#define TABLE64_TEST_HI 6
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/* default register test */
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static struct igb_reg_test reg_test_82575[] = {
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{ E1000_FCAL, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_FCAH, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
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{ E1000_FCT, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
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{ E1000_VET, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
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{ E1000_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
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/* 82576 reg test */
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static struct igb_reg_test reg_test_82576[] = {
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{ E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
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{ E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
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{ E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
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{ E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
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{ E1000_RDBAL(4), 0x40, 8, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
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{ E1000_RDBAH(4), 0x40, 8, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_RDLEN(4), 0x40, 8, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
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/* Enable all four RX queues before testing. */
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{ E1000_RXDCTL(0), 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
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{ E1000_RXDCTL(0), 0x100, 1, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
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/* RDH is read-only for 82576, only test RDT. */
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{ E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
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{ E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
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{ E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
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{ E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
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{ E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
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{ E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
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{ E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
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{ E1000_TDBAL(4), 0x40, 8, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
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{ E1000_TDBAH(4), 0x40, 8, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_TDLEN(4), 0x40, 8, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
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{ E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
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{ E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
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{ E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
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{ E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
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{ E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
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{ E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
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{ E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ 0, 0, 0, 0 }
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};
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/* 82575 register test */
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static struct igb_reg_test reg_test_82575[] = {
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{ E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
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{ E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
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{ E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
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{ E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
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/* Enable all four RX queues before testing. */
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{ E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
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/* RDH is read-only for 82575, only test RDT. */
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{ E1000_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
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{ E1000_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
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{ E1000_FCRTH, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
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{ E1000_FCTTV, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
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{ E1000_TIPG, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
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{ E1000_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
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{ E1000_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
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{ E1000_RCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
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{ E1000_RCTL, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
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{ E1000_RCTL, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
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{ E1000_TCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
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{ E1000_TXCW, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
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{ E1000_RA, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_RA, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
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{ E1000_MTA, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
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{ E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
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{ E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
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{ E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
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{ E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
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{ E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
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{ E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
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{ E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
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{ E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
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{ E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
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{ E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
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{ E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
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{ E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
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{ E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
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{ E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
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{ 0, 0, 0, 0 }
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};
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@@ -937,7 +976,15 @@ static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
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u32 i, toggle;
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toggle = 0x7FFFF3FF;
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test = reg_test_82575;
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switch (adapter->hw.mac.type) {
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case e1000_82576:
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test = reg_test_82576;
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break;
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default:
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test = reg_test_82575;
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break;
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}
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/* Because the status register is such a special case,
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* we handle it separately from the rest of the register
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@@ -964,19 +1011,19 @@ static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
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for (i = 0; i < test->array_len; i++) {
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switch (test->test_type) {
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case PATTERN_TEST:
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REG_PATTERN_TEST(test->reg + (i * 0x100),
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REG_PATTERN_TEST(test->reg + (i * test->reg_offset),
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test->mask,
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test->write);
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break;
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case SET_READ_TEST:
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REG_SET_AND_CHECK(test->reg + (i * 0x100),
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REG_SET_AND_CHECK(test->reg + (i * test->reg_offset),
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test->mask,
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test->write);
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break;
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case WRITE_NO_TEST:
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writel(test->write,
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(adapter->hw.hw_addr + test->reg)
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+ (i * 0x100));
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+ (i * test->reg_offset));
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break;
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case TABLE32_TEST:
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REG_PATTERN_TEST(test->reg + (i * 4),
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@@ -1392,13 +1439,39 @@ static int igb_set_phy_loopback(struct igb_adapter *adapter)
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static int igb_setup_loopback_test(struct igb_adapter *adapter)
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{
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struct e1000_hw *hw = &adapter->hw;
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u32 rctl;
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u32 reg;
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if (hw->phy.media_type == e1000_media_type_fiber ||
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hw->phy.media_type == e1000_media_type_internal_serdes) {
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rctl = rd32(E1000_RCTL);
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rctl |= E1000_RCTL_LBM_TCVR;
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wr32(E1000_RCTL, rctl);
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reg = rd32(E1000_RCTL);
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reg |= E1000_RCTL_LBM_TCVR;
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wr32(E1000_RCTL, reg);
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wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
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reg = rd32(E1000_CTRL);
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reg &= ~(E1000_CTRL_RFCE |
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E1000_CTRL_TFCE |
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E1000_CTRL_LRST);
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reg |= E1000_CTRL_SLU |
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E1000_CTRL_FD;
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wr32(E1000_CTRL, reg);
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/* Unset switch control to serdes energy detect */
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reg = rd32(E1000_CONNSW);
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reg &= ~E1000_CONNSW_ENRGSRC;
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wr32(E1000_CONNSW, reg);
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/* Set PCS register for forced speed */
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reg = rd32(E1000_PCS_LCTL);
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reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
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reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
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E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
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E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
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E1000_PCS_LCTL_FSD | /* Force Speed */
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E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
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wr32(E1000_PCS_LCTL, reg);
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return 0;
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} else if (hw->phy.media_type == e1000_media_type_copper) {
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return igb_set_phy_loopback(adapter);
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@@ -1654,10 +1727,13 @@ static int igb_wol_exclusion(struct igb_adapter *adapter,
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switch (hw->device_id) {
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case E1000_DEV_ID_82575GB_QUAD_COPPER:
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case E1000_DEV_ID_82576_QUAD_COPPER:
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/* WoL not supported */
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wol->supported = 0;
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break;
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case E1000_DEV_ID_82575EB_FIBER_SERDES:
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case E1000_DEV_ID_82576_FIBER:
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case E1000_DEV_ID_82576_SERDES:
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/* Wake events not supported on port B */
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if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
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wol->supported = 0;
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