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drm/amdgpu: change ELM/BAF to Polaris10/Polaris11

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Adjust to preferred code names.

Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Этот коммит содержится в:
Flora Cui
2016-03-14 18:33:29 -04:00
коммит произвёл Alex Deucher
родитель a3ad7a9ad8
Коммит 2cc0c0b5cd
35 изменённых файлов: 1447 добавлений и 1262 удалений
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4
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
Просмотреть файл

@@ -9,8 +9,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
tonga_hwmgr.o pppcielanes.o tonga_thermal.o\
fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
fiji_clockpowergating.o fiji_thermal.o \
ellesmere_hwmgr.o ellesmere_powertune.o ellesmere_thermal.o \
ellesmere_clockpowergating.o
polaris10_hwmgr.o polaris10_powertune.o polaris10_thermal.o \
polaris10_clockpowergating.o
AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))

62
drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h
Просмотреть файл

@@ -1,62 +0,0 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef ELLESMERE_DYN_DEFAULTS_H
#define ELLESMERE_DYN_DEFAULTS_H
enum Ellesmeredpm_TrendDetection {
EllesmereAdpm_TrendDetection_AUTO,
EllesmereAdpm_TrendDetection_UP,
EllesmereAdpm_TrendDetection_DOWN
};
typedef enum Ellesmeredpm_TrendDetection Ellesmeredpm_TrendDetection;
/* We need to fill in the default values */
#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT1 0x000400
#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT2 0xC00080
#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT3 0xC00200
#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT4 0xC01680
#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT5 0xC00033
#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT6 0xC00033
#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT7 0x3FFFC000
#define PPELLESMERE_THERMALPROTECTCOUNTER_DFLT 0x200
#define PPELLESMERE_STATICSCREENTHRESHOLDUNIT_DFLT 0
#define PPELLESMERE_STATICSCREENTHRESHOLD_DFLT 0x00C8
#define PPELLESMERE_GFXIDLECLOCKSTOPTHRESHOLD_DFLT 0x200
#define PPELLESMERE_REFERENCEDIVIDER_DFLT 4
#define PPELLESMERE_ULVVOLTAGECHANGEDELAY_DFLT 1687
#define PPELLESMERE_CGULVPARAMETER_DFLT 0x00040035
#define PPELLESMERE_CGULVCONTROL_DFLT 0x00007450
#define PPELLESMERE_TARGETACTIVITY_DFLT 50
#define PPELLESMERE_MCLK_TARGETACTIVITY_DFLT 10
#endif

8
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
Просмотреть файл

@@ -34,7 +34,7 @@
extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr);
int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
{
@@ -68,9 +68,9 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
case CHIP_FIJI:
fiji_hwmgr_init(hwmgr);
break;
case CHIP_BAFFIN:
case CHIP_ELLESMERE:
ellesemere_hwmgr_init(hwmgr);
case CHIP_POLARIS11:
case CHIP_POLARIS10:
polaris10_hwmgr_init(hwmgr);
break;
default:
return -EINVAL;

62
drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
Просмотреть файл

@@ -21,9 +21,9 @@
*
*/
#include "ellesmere_clockpowergating.h"
#include "polaris10_clockpowergating.h"
int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
int polaris10_phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
if (phm_cf_want_uvd_power_gating(hwmgr))
return smum_send_msg_to_smc(hwmgr->smumgr,
@@ -31,7 +31,7 @@ int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
return 0;
}
int ellesmere_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
int polaris10_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
{
if (phm_cf_want_uvd_power_gating(hwmgr)) {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@@ -47,7 +47,7 @@ int ellesmere_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
return 0;
}
int ellesmere_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
int polaris10_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
{
if (phm_cf_want_vce_power_gating(hwmgr))
return smum_send_msg_to_smc(hwmgr->smumgr,
@@ -55,7 +55,7 @@ int ellesmere_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
return 0;
}
int ellesmere_phm_powerup_vce(struct pp_hwmgr *hwmgr)
int polaris10_phm_powerup_vce(struct pp_hwmgr *hwmgr)
{
if (phm_cf_want_vce_power_gating(hwmgr))
return smum_send_msg_to_smc(hwmgr->smumgr,
@@ -63,7 +63,7 @@ int ellesmere_phm_powerup_vce(struct pp_hwmgr *hwmgr)
return 0;
}
int ellesmere_phm_powerdown_samu(struct pp_hwmgr *hwmgr)
int polaris10_phm_powerdown_samu(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SamuPowerGating))
@@ -72,7 +72,7 @@ int ellesmere_phm_powerdown_samu(struct pp_hwmgr *hwmgr)
return 0;
}
int ellesmere_phm_powerup_samu(struct pp_hwmgr *hwmgr)
int polaris10_phm_powerup_samu(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SamuPowerGating))
@@ -81,24 +81,24 @@ int ellesmere_phm_powerup_samu(struct pp_hwmgr *hwmgr)
return 0;
}
int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
int polaris10_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
{
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
data->uvd_power_gated = false;
data->vce_power_gated = false;
data->samu_power_gated = false;
ellesmere_phm_powerup_uvd(hwmgr);
ellesmere_phm_powerup_vce(hwmgr);
ellesmere_phm_powerup_samu(hwmgr);
polaris10_phm_powerup_uvd(hwmgr);
polaris10_phm_powerup_vce(hwmgr);
polaris10_phm_powerup_samu(hwmgr);
return 0;
}
int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
{
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
if (data->uvd_power_gated == bgate)
return 0;
@@ -106,34 +106,34 @@ int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
data->uvd_power_gated = bgate;
if (bgate) {
ellesmere_update_uvd_dpm(hwmgr, true);
ellesmere_phm_powerdown_uvd(hwmgr);
polaris10_update_uvd_dpm(hwmgr, true);
polaris10_phm_powerdown_uvd(hwmgr);
} else {
ellesmere_phm_powerup_uvd(hwmgr);
ellesmere_update_uvd_dpm(hwmgr, false);
polaris10_phm_powerup_uvd(hwmgr);
polaris10_update_uvd_dpm(hwmgr, false);
}
return 0;
}
int ellesmere_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
{
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
if (data->vce_power_gated == bgate)
return 0;
if (bgate)
ellesmere_phm_powerdown_vce(hwmgr);
polaris10_phm_powerdown_vce(hwmgr);
else
ellesmere_phm_powerup_vce(hwmgr);
polaris10_phm_powerup_vce(hwmgr);
return 0;
}
int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
int polaris10_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
{
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
if (data->samu_power_gated == bgate)
return 0;
@@ -141,17 +141,17 @@ int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
data->samu_power_gated = bgate;
if (bgate) {
ellesmere_update_samu_dpm(hwmgr, true);
ellesmere_phm_powerdown_samu(hwmgr);
polaris10_update_samu_dpm(hwmgr, true);
polaris10_phm_powerdown_samu(hwmgr);
} else {
ellesmere_phm_powerup_samu(hwmgr);
ellesmere_update_samu_dpm(hwmgr, false);
polaris10_phm_powerup_samu(hwmgr);
polaris10_update_samu_dpm(hwmgr, false);
}
return 0;
}
int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
int polaris10_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
const uint32_t *msg_id)
{
PPSMC_Msg msg;
@@ -399,11 +399,11 @@ int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
return 0;
}
/* This function is for Baffin only for now,
/* This function is for Polaris11 only for now,
* Powerplay will only control the static per CU Power Gating.
* Dynamic per CU Power Gating will be done in gfx.
*/
int ellesmere_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
int polaris10_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
{
struct cgs_system_info sys_info = {0};
uint32_t active_cus;

24
drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h
Просмотреть файл

@@ -21,20 +21,20 @@
*
*/
#ifndef _ELLESMERE_CLOCK_POWER_GATING_H_
#define _ELLESMERE_CLOCK_POWER_GATING_H_
#ifndef _POLARIS10_CLOCK_POWER_GATING_H_
#define _POLARIS10_CLOCK_POWER_GATING_H_
#include "ellesmere_hwmgr.h"
#include "polaris10_hwmgr.h"
#include "pp_asicblocks.h"
int ellesmere_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
int ellesmere_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
int polaris10_phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
int polaris10_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
int polaris10_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
int polaris10_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
int polaris10_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
const uint32_t *msg_id);
int ellesmere_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable);
int polaris10_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable);
#endif /* _ELLESMERE_CLOCK_POWER_GATING_H_ */
#endif /* _POLARIS10_CLOCK_POWER_GATING_H_ */

62
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h Обычный файл
Просмотреть файл

@@ -0,0 +1,62 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef POLARIS10_DYN_DEFAULTS_H
#define POLARIS10_DYN_DEFAULTS_H
enum Polaris10dpm_TrendDetection {
Polaris10Adpm_TrendDetection_AUTO,
Polaris10Adpm_TrendDetection_UP,
Polaris10Adpm_TrendDetection_DOWN
};
typedef enum Polaris10dpm_TrendDetection Polaris10dpm_TrendDetection;
/* We need to fill in the default values */
#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1 0x000400
#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2 0xC00080
#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3 0xC00200
#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4 0xC01680
#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5 0xC00033
#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6 0xC00033
#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7 0x3FFFC000
#define PPPOLARIS10_THERMALPROTECTCOUNTER_DFLT 0x200
#define PPPOLARIS10_STATICSCREENTHRESHOLDUNIT_DFLT 0
#define PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT 0x00C8
#define PPPOLARIS10_GFXIDLECLOCKSTOPTHRESHOLD_DFLT 0x200
#define PPPOLARIS10_REFERENCEDIVIDER_DFLT 4
#define PPPOLARIS10_ULVVOLTAGECHANGEDELAY_DFLT 1687
#define PPPOLARIS10_CGULVPARAMETER_DFLT 0x00040035
#define PPPOLARIS10_CGULVCONTROL_DFLT 0x00007450
#define PPPOLARIS10_TARGETACTIVITY_DFLT 50
#define PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT 10
#endif

1293
drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
Просмотреть файл

Разница между файлами не показана из-за своего большого размера Загрузить разницу

178
drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
Просмотреть файл

@@ -21,81 +21,81 @@
*
*/
#ifndef ELLESMERE_HWMGR_H
#define ELLESMERE_HWMGR_H
#ifndef POLARIS10_HWMGR_H
#define POLARIS10_HWMGR_H
#include "hwmgr.h"
#include "smu74.h"
#include "smu74_discrete.h"
#include "ppatomctrl.h"
#include "ellesmere_ppsmc.h"
#include "ellesmere_powertune.h"
#include "polaris10_ppsmc.h"
#include "polaris10_powertune.h"
#define ELLESMERE_MAX_HARDWARE_POWERLEVELS 2
#define POLARIS10_MAX_HARDWARE_POWERLEVELS 2
#define ELLESMERE_VOLTAGE_CONTROL_NONE 0x0
#define ELLESMERE_VOLTAGE_CONTROL_BY_GPIO 0x1
#define ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 0x2
#define ELLESMERE_VOLTAGE_CONTROL_MERGED 0x3
#define POLARIS10_VOLTAGE_CONTROL_NONE 0x0
#define POLARIS10_VOLTAGE_CONTROL_BY_GPIO 0x1
#define POLARIS10_VOLTAGE_CONTROL_BY_SVID2 0x2
#define POLARIS10_VOLTAGE_CONTROL_MERGED 0x3
#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
#define DPMTABLE_UPDATE_SCLK 0x00000004
#define DPMTABLE_UPDATE_MCLK 0x00000008
struct ellesmere_performance_level {
struct polaris10_performance_level {
uint32_t memory_clock;
uint32_t engine_clock;
uint16_t pcie_gen;
uint16_t pcie_lane;
};
struct ellesmere_uvd_clocks {
struct polaris10_uvd_clocks {
uint32_t vclk;
uint32_t dclk;
};
struct ellesmere_vce_clocks {
struct polaris10_vce_clocks {
uint32_t evclk;
uint32_t ecclk;
};
struct ellesmere_power_state {
struct polaris10_power_state {
uint32_t magic;
struct ellesmere_uvd_clocks uvd_clks;
struct ellesmere_vce_clocks vce_clks;
struct polaris10_uvd_clocks uvd_clks;
struct polaris10_vce_clocks vce_clks;
uint32_t sam_clk;
uint16_t performance_level_count;
bool dc_compatible;
uint32_t sclk_threshold;
struct ellesmere_performance_level performance_levels[ELLESMERE_MAX_HARDWARE_POWERLEVELS];
struct polaris10_performance_level performance_levels[POLARIS10_MAX_HARDWARE_POWERLEVELS];
};
struct ellesmere_dpm_level {
struct polaris10_dpm_level {
bool enabled;
uint32_t value;
uint32_t param1;
};
#define ELLESMERE_MAX_DEEPSLEEP_DIVIDER_ID 5
#define POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID 5
#define MAX_REGULAR_DPM_NUMBER 8
#define ELLESMERE_MINIMUM_ENGINE_CLOCK 2500
#define POLARIS10_MINIMUM_ENGINE_CLOCK 2500
struct ellesmere_single_dpm_table {
struct polaris10_single_dpm_table {
uint32_t count;
struct ellesmere_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
struct polaris10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
};
struct ellesmere_dpm_table {
struct ellesmere_single_dpm_table sclk_table;
struct ellesmere_single_dpm_table mclk_table;
struct ellesmere_single_dpm_table pcie_speed_table;
struct ellesmere_single_dpm_table vddc_table;
struct ellesmere_single_dpm_table vddci_table;
struct ellesmere_single_dpm_table mvdd_table;
struct polaris10_dpm_table {
struct polaris10_single_dpm_table sclk_table;
struct polaris10_single_dpm_table mclk_table;
struct polaris10_single_dpm_table pcie_speed_table;
struct polaris10_single_dpm_table vddc_table;
struct polaris10_single_dpm_table vddci_table;
struct polaris10_single_dpm_table mvdd_table;
};
struct ellesmere_clock_registers {
struct polaris10_clock_registers {
uint32_t vCG_SPLL_FUNC_CNTL;
uint32_t vCG_SPLL_FUNC_CNTL_2;
uint32_t vCG_SPLL_FUNC_CNTL_3;
@@ -116,19 +116,19 @@ struct ellesmere_clock_registers {
#define DISABLE_MC_LOADMICROCODE 1
#define DISABLE_MC_CFGPROGRAMMING 2
struct ellesmere_voltage_smio_registers {
struct polaris10_voltage_smio_registers {
uint32_t vS0_VID_LOWER_SMIO_CNTL;
};
#define ELLESMERE_MAX_LEAKAGE_COUNT 8
#define POLARIS10_MAX_LEAKAGE_COUNT 8
struct ellesmere_leakage_voltage {
struct polaris10_leakage_voltage {
uint16_t count;
uint16_t leakage_id[ELLESMERE_MAX_LEAKAGE_COUNT];
uint16_t actual_voltage[ELLESMERE_MAX_LEAKAGE_COUNT];
uint16_t leakage_id[POLARIS10_MAX_LEAKAGE_COUNT];
uint16_t actual_voltage[POLARIS10_MAX_LEAKAGE_COUNT];
};
struct ellesmere_vbios_boot_state {
struct polaris10_vbios_boot_state {
uint16_t mvdd_bootup_value;
uint16_t vddc_bootup_value;
uint16_t vddci_bootup_value;
@@ -139,19 +139,19 @@ struct ellesmere_vbios_boot_state {
};
/* Ultra Low Voltage parameter structure */
struct ellesmere_ulv_parm {
struct polaris10_ulv_parm {
bool ulv_supported;
uint32_t cg_ulv_parameter;
uint32_t ulv_volt_change_delay;
struct ellesmere_performance_level ulv_power_level;
struct polaris10_performance_level ulv_power_level;
};
struct ellesmere_display_timing {
struct polaris10_display_timing {
uint32_t min_clock_in_sr;
uint32_t num_existing_displays;
};
struct ellesmere_dpmlevel_enable_mask {
struct polaris10_dpmlevel_enable_mask {
uint32_t uvd_dpm_enable_mask;
uint32_t vce_dpm_enable_mask;
uint32_t acp_dpm_enable_mask;
@@ -161,22 +161,22 @@ struct ellesmere_dpmlevel_enable_mask {
uint32_t pcie_dpm_enable_mask;
};
struct ellesmere_pcie_perf_range {
struct polaris10_pcie_perf_range {
uint16_t max;
uint16_t min;
};
struct ellesmere_range_table {
struct polaris10_range_table {
uint32_t trans_lower_frequency; /* in 10khz */
uint32_t trans_upper_frequency;
};
struct ellesmere_hwmgr {
struct ellesmere_dpm_table dpm_table;
struct ellesmere_dpm_table golden_dpm_table;
struct polaris10_hwmgr {
struct polaris10_dpm_table dpm_table;
struct polaris10_dpm_table golden_dpm_table;
SMU74_Discrete_DpmTable smc_state_table;
struct SMU74_Discrete_Ulv ulv_setting;
struct ellesmere_range_table range_table[NUM_SCLK_RANGE];
struct polaris10_range_table range_table[NUM_SCLK_RANGE];
uint32_t voting_rights_clients0;
uint32_t voting_rights_clients1;
uint32_t voting_rights_clients2;
@@ -192,8 +192,8 @@ struct ellesmere_hwmgr {
uint32_t active_auto_throttle_sources;
struct ellesmere_clock_registers clock_registers;
struct ellesmere_voltage_smio_registers voltage_smio_registers;
struct polaris10_clock_registers clock_registers;
struct polaris10_voltage_smio_registers voltage_smio_registers;
bool is_memory_gddr5;
uint16_t acpi_vddc;
@@ -203,8 +203,8 @@ struct ellesmere_hwmgr {
uint32_t pcie_gen_cap;
uint32_t pcie_lane_cap;
uint32_t pcie_spc_cap;
struct ellesmere_leakage_voltage vddc_leakage;
struct ellesmere_leakage_voltage Vddci_leakage;
struct polaris10_leakage_voltage vddc_leakage;
struct polaris10_leakage_voltage Vddci_leakage;
uint32_t mvdd_control;
uint32_t vddc_mask_low;
@@ -218,7 +218,7 @@ struct ellesmere_hwmgr {
uint32_t mclk_edc_enable_threshold;
uint32_t mclk_edcwr_enable_threshold;
bool is_uvd_enabled;
struct ellesmere_vbios_boot_state vbios_boot_state;
struct polaris10_vbios_boot_state vbios_boot_state;
bool pcie_performance_request;
bool battery_state;
@@ -250,7 +250,7 @@ struct ellesmere_hwmgr {
bool performance_request_registered;
/* ---- Low Power Features ---- */
struct ellesmere_ulv_parm ulv;
struct polaris10_ulv_parm ulv;
/* ---- CAC Stuff ---- */
uint32_t cac_table_start;
@@ -264,7 +264,7 @@ struct ellesmere_hwmgr {
bool enable_tdc_limit_feature;
bool enable_pkg_pwr_tracking_feature;
bool disable_uvd_power_tune_feature;
struct ellesmere_pt_defaults *power_tune_defaults;
struct polaris10_pt_defaults *power_tune_defaults;
struct SMU74_Discrete_PmFuses power_tune_table;
uint32_t dte_tj_offset;
uint32_t fast_watermark_threshold;
@@ -273,20 +273,20 @@ struct ellesmere_hwmgr {
bool vddc_phase_shed_control;
/* ---- DI/DT ---- */
struct ellesmere_display_timing display_timing;
struct polaris10_display_timing display_timing;
uint32_t bif_sclk_table[SMU74_MAX_LEVELS_LINK];
/* ---- Thermal Temperature Setting ---- */
struct ellesmere_dpmlevel_enable_mask dpm_level_enable_mask;
struct polaris10_dpmlevel_enable_mask dpm_level_enable_mask;
uint32_t need_update_smu7_dpm_table;
uint32_t sclk_dpm_key_disabled;
uint32_t mclk_dpm_key_disabled;
uint32_t pcie_dpm_key_disabled;
uint32_t min_engine_clocks;
struct ellesmere_pcie_perf_range pcie_gen_performance;
struct ellesmere_pcie_perf_range pcie_lane_performance;
struct ellesmere_pcie_perf_range pcie_gen_power_saving;
struct ellesmere_pcie_perf_range pcie_lane_power_saving;
struct polaris10_pcie_perf_range pcie_gen_performance;
struct polaris10_pcie_perf_range pcie_lane_performance;
struct polaris10_pcie_perf_range pcie_gen_power_saving;
struct polaris10_pcie_perf_range pcie_lane_power_saving;
bool use_pcie_performance_levels;
bool use_pcie_power_saving_levels;
uint32_t activity_target[SMU74_MAX_LEVELS_GRAPHICS];
@@ -312,43 +312,43 @@ struct ellesmere_hwmgr {
};
/* To convert to Q8.8 format for firmware */
#define ELLESMERE_Q88_FORMAT_CONVERSION_UNIT 256
#define POLARIS10_Q88_FORMAT_CONVERSION_UNIT 256
enum Ellesmere_I2CLineID {
Ellesmere_I2CLineID_DDC1 = 0x90,
Ellesmere_I2CLineID_DDC2 = 0x91,
Ellesmere_I2CLineID_DDC3 = 0x92,
Ellesmere_I2CLineID_DDC4 = 0x93,
Ellesmere_I2CLineID_DDC5 = 0x94,
Ellesmere_I2CLineID_DDC6 = 0x95,
Ellesmere_I2CLineID_SCLSDA = 0x96,
Ellesmere_I2CLineID_DDCVGA = 0x97
enum Polaris10_I2CLineID {
Polaris10_I2CLineID_DDC1 = 0x90,
Polaris10_I2CLineID_DDC2 = 0x91,
Polaris10_I2CLineID_DDC3 = 0x92,
Polaris10_I2CLineID_DDC4 = 0x93,
Polaris10_I2CLineID_DDC5 = 0x94,
Polaris10_I2CLineID_DDC6 = 0x95,
Polaris10_I2CLineID_SCLSDA = 0x96,
Polaris10_I2CLineID_DDCVGA = 0x97
};
#define ELLESMERE_I2C_DDC1DATA 0
#define ELLESMERE_I2C_DDC1CLK 1
#define ELLESMERE_I2C_DDC2DATA 2
#define ELLESMERE_I2C_DDC2CLK 3
#define ELLESMERE_I2C_DDC3DATA 4
#define ELLESMERE_I2C_DDC3CLK 5
#define ELLESMERE_I2C_SDA 40
#define ELLESMERE_I2C_SCL 41
#define ELLESMERE_I2C_DDC4DATA 65
#define ELLESMERE_I2C_DDC4CLK 66
#define ELLESMERE_I2C_DDC5DATA 0x48
#define ELLESMERE_I2C_DDC5CLK 0x49
#define ELLESMERE_I2C_DDC6DATA 0x4a
#define ELLESMERE_I2C_DDC6CLK 0x4b
#define ELLESMERE_I2C_DDCVGADATA 0x4c
#define ELLESMERE_I2C_DDCVGACLK 0x4d
#define POLARIS10_I2C_DDC1DATA 0
#define POLARIS10_I2C_DDC1CLK 1
#define POLARIS10_I2C_DDC2DATA 2
#define POLARIS10_I2C_DDC2CLK 3
#define POLARIS10_I2C_DDC3DATA 4
#define POLARIS10_I2C_DDC3CLK 5
#define POLARIS10_I2C_SDA 40
#define POLARIS10_I2C_SCL 41
#define POLARIS10_I2C_DDC4DATA 65
#define POLARIS10_I2C_DDC4CLK 66
#define POLARIS10_I2C_DDC5DATA 0x48
#define POLARIS10_I2C_DDC5CLK 0x49
#define POLARIS10_I2C_DDC6DATA 0x4a
#define POLARIS10_I2C_DDC6CLK 0x4b
#define POLARIS10_I2C_DDCVGADATA 0x4c
#define POLARIS10_I2C_DDCVGACLK 0x4d
#define ELLESMERE_UNUSED_GPIO_PIN 0x7F
#define POLARIS10_UNUSED_GPIO_PIN 0x7F
int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr);
int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr);
int ellesmere_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
int ellesmere_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
int ellesmere_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
#endif

106
drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
Просмотреть файл

@@ -23,16 +23,16 @@
#include "hwmgr.h"
#include "smumgr.h"
#include "ellesmere_hwmgr.h"
#include "ellesmere_powertune.h"
#include "ellesmere_smumgr.h"
#include "polaris10_hwmgr.h"
#include "polaris10_powertune.h"
#include "polaris10_smumgr.h"
#include "smu74_discrete.h"
#include "pp_debug.h"
#define VOLTAGE_SCALE 4
#define POWERTUNE_DEFAULT_SET_MAX 1
struct ellesmere_pt_defaults ellesmere_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
/* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
* TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
{ 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
@@ -40,27 +40,27 @@ struct ellesmere_pt_defaults ellesmere_power_tune_data_set_array[POWERTUNE_DEFAU
{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
};
void ellesmere_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
{
struct ellesmere_hwmgr *ellesmere_hwmgr = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *polaris10_hwmgr = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
if (table_info &&
table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
table_info->cac_dtp_table->usPowerTuneDataSetID)
ellesmere_hwmgr->power_tune_defaults =
&ellesmere_power_tune_data_set_array
polaris10_hwmgr->power_tune_defaults =
&polaris10_power_tune_data_set_array
[table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
else
ellesmere_hwmgr->power_tune_defaults = &ellesmere_power_tune_data_set_array[0];
polaris10_hwmgr->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
}
int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
{
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct ellesmere_pt_defaults *defaults = data->power_tune_defaults;
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
SMU74_Discrete_DpmTable *dpm_table = &(data->smc_state_table);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -101,10 +101,10 @@ int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
return 0;
}
static int ellesmere_populate_svi_load_line(struct pp_hwmgr *hwmgr)
static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
{
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct ellesmere_pt_defaults *defaults = data->power_tune_defaults;
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
@@ -114,13 +114,13 @@ static int ellesmere_populate_svi_load_line(struct pp_hwmgr *hwmgr)
return 0;
}
static int ellesmere_populate_tdc_limit(struct pp_hwmgr *hwmgr)
static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
{
uint16_t tdc_limit;
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct ellesmere_pt_defaults *defaults = data->power_tune_defaults;
struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
data->power_tune_table.TDC_VDDC_PkgLimit =
@@ -132,13 +132,13 @@ static int ellesmere_populate_tdc_limit(struct pp_hwmgr *hwmgr)
return 0;
}
static int ellesmere_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
{
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct ellesmere_pt_defaults *defaults = data->power_tune_defaults;
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
uint32_t temp;
if (ellesmere_read_smc_sram_dword(hwmgr->smumgr,
if (polaris10_read_smc_sram_dword(hwmgr->smumgr,
fuse_table_offset +
offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
(uint32_t *)&temp, data->sram_end))
@@ -156,10 +156,10 @@ static int ellesmere_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_of
return 0;
}
static int ellesmere_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
{
int i;
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
/* Currently not used. Set all to zero. */
for (i = 0; i < 16; i++)
@@ -168,9 +168,9 @@ static int ellesmere_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
return 0;
}
static int ellesmere_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
{
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
|| 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
@@ -182,10 +182,10 @@ static int ellesmere_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
return 0;
}
static int ellesmere_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
{
int i;
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
/* Currently not used. Set all to zero. */
for (i = 0; i < 16; i++)
@@ -194,14 +194,14 @@ static int ellesmere_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
return 0;
}
static int ellesmere_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
static int polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
{
return 0;
}
static int ellesmere_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
{
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
uint16_t hi_sidd = data->power_tune_table.BapmVddCBaseLeakageHiSidd;
@@ -219,14 +219,14 @@ static int ellesmere_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr
return 0;
}
int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr)
int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
{
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
uint32_t pm_fuse_table_offset;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment)) {
if (ellesmere_read_smc_sram_dword(hwmgr->smumgr,
if (polaris10_read_smc_sram_dword(hwmgr->smumgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, PmFuseTable),
&pm_fuse_table_offset, data->sram_end))
@@ -234,47 +234,47 @@ int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr)
"Attempt to get pm_fuse_table_offset Failed!",
return -EINVAL);
if (ellesmere_populate_svi_load_line(hwmgr))
if (polaris10_populate_svi_load_line(hwmgr))
PP_ASSERT_WITH_CODE(false,
"Attempt to populate SviLoadLine Failed!",
return -EINVAL);
if (ellesmere_populate_tdc_limit(hwmgr))
if (polaris10_populate_tdc_limit(hwmgr))
PP_ASSERT_WITH_CODE(false,
"Attempt to populate TDCLimit Failed!", return -EINVAL);
if (ellesmere_populate_dw8(hwmgr, pm_fuse_table_offset))
if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
PP_ASSERT_WITH_CODE(false,
"Attempt to populate TdcWaterfallCtl, "
"LPMLTemperature Min and Max Failed!",
return -EINVAL);
if (0 != ellesmere_populate_temperature_scaler(hwmgr))
if (0 != polaris10_populate_temperature_scaler(hwmgr))
PP_ASSERT_WITH_CODE(false,
"Attempt to populate LPMLTemperatureScaler Failed!",
return -EINVAL);
if (ellesmere_populate_fuzzy_fan(hwmgr))
if (polaris10_populate_fuzzy_fan(hwmgr))
PP_ASSERT_WITH_CODE(false,
"Attempt to populate Fuzzy Fan Control parameters Failed!",
return -EINVAL);
if (ellesmere_populate_gnb_lpml(hwmgr))
if (polaris10_populate_gnb_lpml(hwmgr))
PP_ASSERT_WITH_CODE(false,
"Attempt to populate GnbLPML Failed!",
return -EINVAL);
if (ellesmere_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
if (polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
PP_ASSERT_WITH_CODE(false,
"Attempt to populate GnbLPML Min and Max Vid Failed!",
return -EINVAL);
if (ellesmere_populate_bapm_vddc_base_leakage_sidd(hwmgr))
if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
PP_ASSERT_WITH_CODE(false,
"Attempt to populate BapmVddCBaseLeakage Hi and Lo "
"Sidd Failed!", return -EINVAL);
if (ellesmere_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
if (polaris10_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
(uint8_t *)&data->power_tune_table,
sizeof(struct SMU74_Discrete_PmFuses), data->sram_end))
PP_ASSERT_WITH_CODE(false,
@@ -284,9 +284,9 @@ int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr)
return 0;
}
int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr)
int polaris10_enable_smc_cac(struct pp_hwmgr *hwmgr)
{
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
int result = 0;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@@ -302,9 +302,9 @@ int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr)
return result;
}
int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
{
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_PkgPwrLimit)
@@ -313,15 +313,15 @@ int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
return 0;
}
static int ellesmere_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp)
static int polaris10_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp)
{
return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr,
PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
}
int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr)
int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr)
{
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
int smc_result;
@@ -363,7 +363,7 @@ int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr)
data->power_containment_features |=
POWERCONTAINMENT_FEATURE_PkgPwrLimit;
if (ellesmere_set_power_limit(hwmgr, default_limit))
if (polaris10_set_power_limit(hwmgr, default_limit))
printk(KERN_ERR "Failed to set Default Power Limit in SMC!");
}
}
@@ -371,7 +371,7 @@ int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr)
return result;
}
int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr)
int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr)
{
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -389,7 +389,7 @@ int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr)
* but message to be 8 bit fraction for messages
*/
target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
result = ellesmere_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
result = polaris10_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
}
return result;

38
drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h
Просмотреть файл

@@ -20,15 +20,15 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef ELLESMERE_POWERTUNE_H
#define ELLESMERE_POWERTUNE_H
#ifndef POLARIS10_POWERTUNE_H
#define POLARIS10_POWERTUNE_H
enum ellesmere_pt_config_reg_type {
ELLESMERE_CONFIGREG_MMR = 0,
ELLESMERE_CONFIGREG_SMC_IND,
ELLESMERE_CONFIGREG_DIDT_IND,
ELLESMERE_CONFIGREG_CACHE,
ELLESMERE_CONFIGREG_MAX
enum polaris10_pt_config_reg_type {
POLARIS10_CONFIGREG_MMR = 0,
POLARIS10_CONFIGREG_SMC_IND,
POLARIS10_CONFIGREG_DIDT_IND,
POLARIS10_CONFIGREG_CACHE,
POLARIS10_CONFIGREG_MAX
};
/* PowerContainment Features */
@@ -36,15 +36,15 @@ enum ellesmere_pt_config_reg_type {
#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
struct ellesmere_pt_config_reg {
struct polaris10_pt_config_reg {
uint32_t offset;
uint32_t mask;
uint32_t shift;
uint32_t value;
enum ellesmere_pt_config_reg_type type;
enum polaris10_pt_config_reg_type type;
};
struct ellesmere_pt_defaults {
struct polaris10_pt_defaults {
uint8_t SviLoadLineEn;
uint8_t SviLoadLineVddC;
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
@@ -58,13 +58,13 @@ struct ellesmere_pt_defaults {
uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
};
void ellesmere_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr);
int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr);
int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr);
int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr);
void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr);
int polaris10_enable_smc_cac(struct pp_hwmgr *hwmgr);
int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr);
int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr);
#endif /* ELLESMERE_POWERTUNE_H */
#endif /* POLARIS10_POWERTUNE_H */

140
drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
Просмотреть файл

@@ -21,14 +21,14 @@
*
*/
#include "ellesmere_thermal.h"
#include "ellesmere_hwmgr.h"
#include "ellesmere_smumgr.h"
#include "ellesmere_ppsmc.h"
#include "polaris10_thermal.h"
#include "polaris10_hwmgr.h"
#include "polaris10_smumgr.h"
#include "polaris10_ppsmc.h"
#include "smu/smu_7_1_3_d.h"
#include "smu/smu_7_1_3_sh_mask.h"
int ellesmere_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
int polaris10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
struct phm_fan_speed_info *fan_speed_info)
{
if (hwmgr->thermal_controller.fanInfo.bNoFan)
@@ -54,7 +54,7 @@ int ellesmere_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
return 0;
}
int ellesmere_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
int polaris10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
uint32_t *speed)
{
uint32_t duty100;
@@ -83,7 +83,7 @@ int ellesmere_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
return 0;
}
int ellesmere_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
int polaris10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
{
uint32_t tach_period;
uint32_t crystal_clock_freq;
@@ -112,7 +112,7 @@ int ellesmere_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed
* mode the fan control mode, 0 default, 1 by percent, 5, by RPM
* @exception Should always succeed.
*/
int ellesmere_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
int polaris10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
{
if (hwmgr->fan_ctrl_is_in_default_mode) {
@@ -138,7 +138,7 @@ int ellesmere_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
* @param hwmgr the address of the powerplay hardware manager.
* @exception Should always succeed.
*/
int ellesmere_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
int polaris10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
{
if (!hwmgr->fan_ctrl_is_in_default_mode) {
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
@@ -151,7 +151,7 @@ int ellesmere_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
return 0;
}
int ellesmere_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
int polaris10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
{
int result;
@@ -186,7 +186,7 @@ int ellesmere_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
}
int ellesmere_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
int polaris10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
{
return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl);
}
@@ -197,7 +197,7 @@ int ellesmere_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
* @param speed is the percentage value (0% - 100%) to be set.
* @exception Fails is the 100% setting appears to be 0.
*/
int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
int polaris10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
uint32_t speed)
{
uint32_t duty100;
@@ -212,7 +212,7 @@ int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl))
ellesmere_fan_ctrl_stop_smc_fan_control(hwmgr);
polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
CG_FDO_CTRL1, FMAX_DUTY100);
@@ -227,7 +227,7 @@ int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
CG_FDO_CTRL0, FDO_STATIC_DUTY, duty);
return ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
return polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
}
/**
@@ -235,7 +235,7 @@ int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
* @param hwmgr the address of the powerplay hardware manager.
* @exception Always succeeds.
*/
int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
int polaris10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
{
int result;
@@ -244,11 +244,11 @@ int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl)) {
result = ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
result = polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
if (!result)
result = ellesmere_fan_ctrl_start_smc_fan_control(hwmgr);
result = polaris10_fan_ctrl_start_smc_fan_control(hwmgr);
} else
result = ellesmere_fan_ctrl_set_default_mode(hwmgr);
result = polaris10_fan_ctrl_set_default_mode(hwmgr);
return result;
}
@@ -259,7 +259,7 @@ int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
* @param speed is the percentage value (min - max) to be set.
* @exception Fails is the speed not lie between min and max.
*/
int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
int polaris10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
{
uint32_t tach_period;
uint32_t crystal_clock_freq;
@@ -273,7 +273,7 @@ int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl))
ellesmere_fan_ctrl_stop_smc_fan_control(hwmgr);
polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
crystal_clock_freq = tonga_get_xclk(hwmgr);
@@ -282,7 +282,7 @@ int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
CG_TACH_STATUS, TACH_PERIOD, tach_period);
return ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
return polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
}
/**
@@ -290,7 +290,7 @@ int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
*
* @param hwmgr The address of the hardware manager.
*/
int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr)
int polaris10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
{
int temp;
@@ -299,7 +299,7 @@ int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr)
/* Bit 9 means the reading is lower than the lowest usable value. */
if (temp & 0x200)
temp = ELLESMERE_THERMAL_MAXIMUM_TEMP_READING;
temp = POLARIS10_THERMAL_MAXIMUM_TEMP_READING;
else
temp = temp & 0x1ff;
@@ -315,12 +315,12 @@ int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr)
* @param range Temperature range to be programmed for high and low alert signals
* @exception PP_Result_BadInput if the input data is not valid.
*/
static int ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
static int polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
uint32_t low_temp, uint32_t high_temp)
{
uint32_t low = ELLESMERE_THERMAL_MINIMUM_ALERT_TEMP *
uint32_t low = POLARIS10_THERMAL_MINIMUM_ALERT_TEMP *
PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
uint32_t high = ELLESMERE_THERMAL_MAXIMUM_ALERT_TEMP *
uint32_t high = POLARIS10_THERMAL_MAXIMUM_ALERT_TEMP *
PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
if (low < low_temp)
@@ -349,7 +349,7 @@ static int ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
*
* @param hwmgr The address of the hardware manager.
*/
static int ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr)
static int polaris10_thermal_initialize(struct pp_hwmgr *hwmgr)
{
if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution)
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
@@ -368,13 +368,13 @@ static int ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr)
*
* @param hwmgr The address of the hardware manager.
*/
static int ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr)
static int polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
{
uint32_t alert;
alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
CG_THERMAL_INT, THERM_INT_MASK);
alert &= ~(ELLESMERE_THERMAL_HIGH_ALERT_MASK | ELLESMERE_THERMAL_LOW_ALERT_MASK);
alert &= ~(POLARIS10_THERMAL_HIGH_ALERT_MASK | POLARIS10_THERMAL_LOW_ALERT_MASK);
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
CG_THERMAL_INT, THERM_INT_MASK, alert);
@@ -386,13 +386,13 @@ static int ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr)
* Disable thermal alerts on the RV770 thermal controller.
* @param hwmgr The address of the hardware manager.
*/
static int ellesmere_thermal_disable_alert(struct pp_hwmgr *hwmgr)
static int polaris10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
{
uint32_t alert;
alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
CG_THERMAL_INT, THERM_INT_MASK);
alert |= (ELLESMERE_THERMAL_HIGH_ALERT_MASK | ELLESMERE_THERMAL_LOW_ALERT_MASK);
alert |= (POLARIS10_THERMAL_HIGH_ALERT_MASK | POLARIS10_THERMAL_LOW_ALERT_MASK);
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
CG_THERMAL_INT, THERM_INT_MASK, alert);
@@ -405,12 +405,12 @@ static int ellesmere_thermal_disable_alert(struct pp_hwmgr *hwmgr)
* Currently just disables alerts.
* @param hwmgr The address of the hardware manager.
*/
int ellesmere_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
int polaris10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
{
int result = ellesmere_thermal_disable_alert(hwmgr);
int result = polaris10_thermal_disable_alert(hwmgr);
if (!hwmgr->thermal_controller.fanInfo.bNoFan)
ellesmere_fan_ctrl_set_default_mode(hwmgr);
polaris10_fan_ctrl_set_default_mode(hwmgr);
return result;
}
@@ -424,10 +424,10 @@ int ellesmere_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
* @param Result the last failure code
* @return result from set temperature range routine
*/
int tf_ellesmere_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
int tf_polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
void *input, void *output, void *storage, int result)
{
struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
uint32_t duty100;
uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
@@ -502,7 +502,7 @@ int tf_ellesmere_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
hwmgr->device, CGS_IND_REG__SMC,
CG_MULT_THERMAL_CTRL, TEMP_SEL);
res = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, data->fan_table_start,
res = polaris10_copy_bytes_to_smc(hwmgr->smumgr, data->fan_table_start,
(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
data->sram_end);
@@ -536,7 +536,7 @@ int tf_ellesmere_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
* @param Result the last failure code
* @return result from set temperature range routine
*/
int tf_ellesmere_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
int tf_polaris10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
void *input, void *output, void *storage, int result)
{
/* If the fantable setup has failed we could have disabled
@@ -546,8 +546,8 @@ int tf_ellesmere_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
*/
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl)) {
ellesmere_fan_ctrl_start_smc_fan_control(hwmgr);
ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
polaris10_fan_ctrl_start_smc_fan_control(hwmgr);
polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
}
return 0;
@@ -562,7 +562,7 @@ int tf_ellesmere_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
* @param Result the last failure code
* @return result from set temperature range routine
*/
int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
int tf_polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
void *input, void *output, void *storage, int result)
{
struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
@@ -570,7 +570,7 @@ int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
if (range == NULL)
return -EINVAL;
return ellesmere_thermal_set_temperature_range(hwmgr, range->min, range->max);
return polaris10_thermal_set_temperature_range(hwmgr, range->min, range->max);
}
/**
@@ -582,10 +582,10 @@ int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
* @param Result the last failure code
* @return result from initialize thermal controller routine
*/
int tf_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr,
int tf_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr,
void *input, void *output, void *storage, int result)
{
return ellesmere_thermal_initialize(hwmgr);
return polaris10_thermal_initialize(hwmgr);
}
/**
@@ -597,10 +597,10 @@ int tf_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr,
* @param Result the last failure code
* @return result from enable alert routine
*/
int tf_ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr,
int tf_polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr,
void *input, void *output, void *storage, int result)
{
return ellesmere_thermal_enable_alert(hwmgr);
return polaris10_thermal_enable_alert(hwmgr);
}
/**
@@ -612,18 +612,18 @@ int tf_ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr,
* @param Result the last failure code
* @return result from disable alert routine
*/
static int tf_ellesmere_thermal_disable_alert(struct pp_hwmgr *hwmgr,
static int tf_polaris10_thermal_disable_alert(struct pp_hwmgr *hwmgr,
void *input, void *output, void *storage, int result)
{
return ellesmere_thermal_disable_alert(hwmgr);
return polaris10_thermal_disable_alert(hwmgr);
}
static int tf_ellesmere_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
static int tf_polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
void *input, void *output, void *storage, int result)
{
int ret;
struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr);
struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS)
return 0;
@@ -639,47 +639,47 @@ static int tf_ellesmere_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
}
static struct phm_master_table_item
ellesmere_thermal_start_thermal_controller_master_list[] = {
{NULL, tf_ellesmere_thermal_initialize},
{NULL, tf_ellesmere_thermal_set_temperature_range},
{NULL, tf_ellesmere_thermal_enable_alert},
{NULL, tf_ellesmere_thermal_avfs_enable},
polaris10_thermal_start_thermal_controller_master_list[] = {
{NULL, tf_polaris10_thermal_initialize},
{NULL, tf_polaris10_thermal_set_temperature_range},
{NULL, tf_polaris10_thermal_enable_alert},
{NULL, tf_polaris10_thermal_avfs_enable},
/* We should restrict performance levels to low before we halt the SMC.
* On the other hand we are still in boot state when we do this
* so it would be pointless.
* If this assumption changes we have to revisit this table.
*/
{NULL, tf_ellesmere_thermal_setup_fan_table},
{NULL, tf_ellesmere_thermal_start_smc_fan_control},
{NULL, tf_polaris10_thermal_setup_fan_table},
{NULL, tf_polaris10_thermal_start_smc_fan_control},
{NULL, NULL}
};
static struct phm_master_table_header
ellesmere_thermal_start_thermal_controller_master = {
polaris10_thermal_start_thermal_controller_master = {
0,
PHM_MasterTableFlag_None,
ellesmere_thermal_start_thermal_controller_master_list
polaris10_thermal_start_thermal_controller_master_list
};
static struct phm_master_table_item
ellesmere_thermal_set_temperature_range_master_list[] = {
{NULL, tf_ellesmere_thermal_disable_alert},
{NULL, tf_ellesmere_thermal_set_temperature_range},
{NULL, tf_ellesmere_thermal_enable_alert},
polaris10_thermal_set_temperature_range_master_list[] = {
{NULL, tf_polaris10_thermal_disable_alert},
{NULL, tf_polaris10_thermal_set_temperature_range},
{NULL, tf_polaris10_thermal_enable_alert},
{NULL, NULL}
};
struct phm_master_table_header
ellesmere_thermal_set_temperature_range_master = {
polaris10_thermal_set_temperature_range_master = {
0,
PHM_MasterTableFlag_None,
ellesmere_thermal_set_temperature_range_master_list
polaris10_thermal_set_temperature_range_master_list
};
int ellesmere_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
int polaris10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
{
if (!hwmgr->thermal_controller.fanInfo.bNoFan)
ellesmere_fan_ctrl_set_default_mode(hwmgr);
polaris10_fan_ctrl_set_default_mode(hwmgr);
return 0;
}
@@ -688,17 +688,17 @@ int ellesmere_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmg
* @param hwmgr The address of the hardware manager.
* @exception Any error code from the low-level communication.
*/
int pp_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr)
int pp_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr)
{
int result;
result = phm_construct_table(hwmgr,
&ellesmere_thermal_set_temperature_range_master,
&polaris10_thermal_set_temperature_range_master,
&(hwmgr->set_temperature_range));
if (!result) {
result = phm_construct_table(hwmgr,
&ellesmere_thermal_start_thermal_controller_master,
&polaris10_thermal_start_thermal_controller_master,
&(hwmgr->start_thermal_controller));
if (result)
phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));

48
drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h
Просмотреть файл

@@ -21,41 +21,41 @@
*
*/
#ifndef _ELLESMERE_THERMAL_H_
#define _ELLESMERE_THERMAL_H_
#ifndef _POLARIS10_THERMAL_H_
#define _POLARIS10_THERMAL_H_
#include "hwmgr.h"
#define ELLESMERE_THERMAL_HIGH_ALERT_MASK 0x1
#define ELLESMERE_THERMAL_LOW_ALERT_MASK 0x2
#define POLARIS10_THERMAL_HIGH_ALERT_MASK 0x1
#define POLARIS10_THERMAL_LOW_ALERT_MASK 0x2
#define ELLESMERE_THERMAL_MINIMUM_TEMP_READING -256
#define ELLESMERE_THERMAL_MAXIMUM_TEMP_READING 255
#define POLARIS10_THERMAL_MINIMUM_TEMP_READING -256
#define POLARIS10_THERMAL_MAXIMUM_TEMP_READING 255
#define ELLESMERE_THERMAL_MINIMUM_ALERT_TEMP 0
#define ELLESMERE_THERMAL_MAXIMUM_ALERT_TEMP 255
#define POLARIS10_THERMAL_MINIMUM_ALERT_TEMP 0
#define POLARIS10_THERMAL_MAXIMUM_ALERT_TEMP 255
#define FDO_PWM_MODE_STATIC 1
#define FDO_PWM_MODE_STATIC_RPM 5
extern int tf_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
extern int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
extern int tf_ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
extern int tf_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
extern int tf_polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
extern int tf_polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
extern int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr);
extern int ellesmere_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
extern int ellesmere_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
extern int ellesmere_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed);
extern int ellesmere_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
extern int ellesmere_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
extern int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
extern int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
extern int pp_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr);
extern int ellesmere_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
extern int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
extern int ellesmere_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
extern int ellesmere_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
extern int polaris10_thermal_get_temperature(struct pp_hwmgr *hwmgr);
extern int polaris10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
extern int polaris10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
extern int polaris10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed);
extern int polaris10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
extern int polaris10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
extern int polaris10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
extern int polaris10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
extern int pp_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr);
extern int polaris10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
extern int polaris10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
extern int polaris10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
extern int polaris10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
extern uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr);
#endif

10
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h
Просмотреть файл

@@ -209,18 +209,18 @@ typedef struct _ATOM_Tonga_PCIE_Table {
ATOM_Tonga_PCIE_Record entries[1]; /* Dynamically allocate entries. */
} ATOM_Tonga_PCIE_Table;
typedef struct _ATOM_Ellesmere_PCIE_Record {
typedef struct _ATOM_Polaris10_PCIE_Record {
UCHAR ucPCIEGenSpeed;
UCHAR usPCIELaneWidth;
UCHAR ucReserved[2];
ULONG ulPCIE_Sclk;
} ATOM_Ellesmere_PCIE_Record;
} ATOM_Polaris10_PCIE_Record;
typedef struct _ATOM_Ellesmere_PCIE_Table {
typedef struct _ATOM_Polaris10_PCIE_Table {
UCHAR ucRevId;
UCHAR ucNumEntries; /* Number of entries. */
ATOM_Ellesmere_PCIE_Record entries[1]; /* Dynamically allocate entries. */
} ATOM_Ellesmere_PCIE_Table;
ATOM_Polaris10_PCIE_Record entries[1]; /* Dynamically allocate entries. */
} ATOM_Polaris10_PCIE_Table;
typedef struct _ATOM_Tonga_MM_Dependency_Record {

4
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
Просмотреть файл

@@ -493,8 +493,8 @@ static int get_pcie_table(
*pp_tonga_pcie_table = pcie_table;
} else {
/* Ellesmere/Baffin and newer. */
const ATOM_Ellesmere_PCIE_Table *atom_pcie_table = (ATOM_Ellesmere_PCIE_Table *)pTable;
/* Polaris10/Polaris11 and newer. */
const ATOM_Polaris10_PCIE_Table *atom_pcie_table = (ATOM_Polaris10_PCIE_Table *)pTable;
PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),
"Invalid PowerPlay Table!", return -1);

12
drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h → drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h
Просмотреть файл

@@ -21,8 +21,8 @@
*
*/
#ifndef ELLESMERE_PP_SMC_H
#define ELLESMERE_PP_SMC_H
#ifndef POLARIS10_PP_SMC_H
#define POLARIS10_PP_SMC_H
#pragma pack(push, 1)
@@ -386,8 +386,16 @@ typedef uint16_t PPSMC_Result;
#define PPSMC_MSG_GFX_CU_PG_ENABLE ((uint16_t) 0x280)
#define PPSMC_MSG_GFX_CU_PG_DISABLE ((uint16_t) 0x281)
#define PPSMC_MSG_GetCurrPkgPwr ((uint16_t) 0x282)
#define PPSMC_MSG_SetGpuPllDfsForSclk ((uint16_t) 0x300)
#define PPSMC_MSG_Didt_Block_Function ((uint16_t) 0x301)
#define PPSMC_MSG_SecureSRBMWrite ((uint16_t) 0x600)
#define PPSMC_MSG_SecureSRBMRead ((uint16_t) 0x601)
#define PPSMC_MSG_SetAddress ((uint16_t) 0x800)
#define PPSMC_MSG_GetData ((uint16_t) 0x801)
#define PPSMC_MSG_SetData ((uint16_t) 0x802)
typedef uint16_t PPSMC_Msg;

4
drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h → drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h
Просмотреть файл

@@ -20,8 +20,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _ELLESMERE_PWRVIRUS_H
#define _ELLESMERE_PWRVIRUS_H
#ifndef _POLARIS10_PWRVIRUS_H
#define _POLARIS10_PWRVIRUS_H
#define mmSMC_IND_INDEX_11 0x01AC
#define mmSMC_IND_DATA_11 0x01AD

42
drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
Просмотреть файл

@@ -705,6 +705,7 @@ struct SMU7_Discrete_Pm_Status_Table {
uint16_t Sclk_dpm_residency[8];
uint16_t Uvd_dpm_residency[8];
uint16_t Vce_dpm_residency[8];
uint16_t Mclk_dpm_residency[4];
uint32_t P_vddci_acc;
uint32_t P_vddr1_acc;
@@ -779,6 +780,47 @@ typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
// DIDT Defines
#define SQ_Enable_MASK 0x1
#define SQ_IR_MASK 0x2
#define SQ_PCC_MASK 0x4
#define SQ_EDC_MASK 0x8
#define TCP_Enable_MASK 0x100
#define TCP_IR_MASK 0x200
#define TCP_PCC_MASK 0x400
#define TCP_EDC_MASK 0x800
#define TD_Enable_MASK 0x10000
#define TD_IR_MASK 0x20000
#define TD_PCC_MASK 0x40000
#define TD_EDC_MASK 0x80000
#define DB_Enable_MASK 0x1000000
#define DB_IR_MASK 0x2000000
#define DB_PCC_MASK 0x4000000
#define DB_EDC_MASK 0x8000000
#define SQ_Enable_SHIFT 0
#define SQ_IR_SHIFT 1
#define SQ_PCC_SHIFT 2
#define SQ_EDC_SHIFT 3
#define TCP_Enable_SHIFT 8
#define TCP_IR_SHIFT 9
#define TCP_PCC_SHIFT 10
#define TCP_EDC_SHIFT 11
#define TD_Enable_SHIFT 16
#define TD_IR_SHIFT 17
#define TD_PCC_SHIFT 18
#define TD_EDC_SHIFT 19
#define DB_Enable_SHIFT 24
#define DB_IR_SHIFT 25
#define DB_PCC_SHIFT 26
#define DB_EDC_SHIFT 27
#pragma pack(pop)

2
drivers/gpu/drm/amd/powerplay/smumgr/Makefile
Просмотреть файл

@@ -2,7 +2,7 @@
# Makefile for the 'smu manager' sub-component of powerplay.
# It provides the smu management services for the driver.
SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o ellesmere_smumgr.o
SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o polaris10_smumgr.o
AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))

244
drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c → drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
Просмотреть файл

@@ -24,7 +24,7 @@
#include "smumgr.h"
#include "smu74.h"
#include "smu_ucode_xfer_vi.h"
#include "ellesmere_smumgr.h"
#include "polaris10_smumgr.h"
#include "smu74_discrete.h"
#include "smu/smu_7_1_3_d.h"
#include "smu/smu_7_1_3_sh_mask.h"
@@ -34,12 +34,12 @@
#include "gca/gfx_8_0_d.h"
#include "bif/bif_5_0_d.h"
#include "bif/bif_5_0_sh_mask.h"
#include "ellesmere_pwrvirus.h"
#include "polaris10_pwrvirus.h"
#include "ppatomctrl.h"
#include "pp_debug.h"
#include "cgs_common.h"
#define ELLESMERE_SMC_SIZE 0x20000
#define POLARIS10_SMC_SIZE 0x20000
#define VOLTAGE_SCALE 4
/* Microcode file is stored in this buffer */
@@ -49,7 +49,7 @@
#define SMC_RAM_END 0x40000
SMU74_Discrete_GraphicsLevel avfs_graphics_level_ellesmere[8] = {
SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
/* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */
/* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
{ 0x3c0fd047, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x30750000, 0, 0, 0, 0, 0, 0, 0 } },
@@ -62,7 +62,7 @@ SMU74_Discrete_GraphicsLevel avfs_graphics_level_ellesmere[8] = {
{ 0xf811d047, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x80380100, 0, 0, 0, 0, 0, 0, 0 } }
};
SMU74_Discrete_MemoryLevel avfs_memory_level_ellesmere = {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00,
SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00,
0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00};
/**
@@ -70,7 +70,7 @@ SMU74_Discrete_MemoryLevel avfs_memory_level_ellesmere = {0x50140000, 0x50140000
* @param smumgr the address of the powerplay hardware manager.
* @param smcAddress the address in the SMC RAM to access.
*/
static int ellesmere_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit)
static int polaris10_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit)
{
PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
@@ -89,7 +89,7 @@ static int ellesmere_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc
* @param src the byte array to copy the bytes to.
* @param byte_count the number of bytes to copy.
*/
int ellesmere_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
int polaris10_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
{
uint32_t data;
uint32_t addr;
@@ -103,7 +103,7 @@ int ellesmere_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_a
addr = smc_start_address;
while (byte_count >= 4) {
ellesmere_read_smc_sram_dword(smumgr, addr, &data, limit);
polaris10_read_smc_sram_dword(smumgr, addr, &data, limit);
*dest = PP_SMC_TO_HOST_UL(data);
@@ -113,7 +113,7 @@ int ellesmere_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_a
}
if (byte_count) {
ellesmere_read_smc_sram_dword(smumgr, addr, &data, limit);
polaris10_read_smc_sram_dword(smumgr, addr, &data, limit);
*pdata = PP_SMC_TO_HOST_UL(data);
/* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */
dest_byte = (uint8_t *)dest;
@@ -132,7 +132,7 @@ int ellesmere_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_a
* @param src the byte array to copy the bytes from.
* @param byte_count the number of bytes to copy.
*/
int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
const uint8_t *src, uint32_t byte_count, uint32_t limit)
{
int result;
@@ -150,7 +150,7 @@ int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
/* Bytes are written into the SMC addres space with the MSB first. */
data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
result = ellesmere_set_smc_sram_address(smumgr, addr, limit);
result = polaris10_set_smc_sram_address(smumgr, addr, limit);
if (0 != result)
return result;
@@ -166,7 +166,7 @@ int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
data = 0;
result = ellesmere_set_smc_sram_address(smumgr, addr, limit);
result = polaris10_set_smc_sram_address(smumgr, addr, limit);
if (0 != result)
return result;
@@ -186,7 +186,7 @@ int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
data |= (original_data & ~((~0UL) << extra_shift));
result = ellesmere_set_smc_sram_address(smumgr, addr, limit);
result = polaris10_set_smc_sram_address(smumgr, addr, limit);
if (0 != result)
return result;
@@ -198,11 +198,11 @@ int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
}
static int ellesmere_program_jump_on_start(struct pp_smumgr *smumgr)
static int polaris10_program_jump_on_start(struct pp_smumgr *smumgr)
{
static unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
ellesmere_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
polaris10_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
return 0;
}
@@ -212,7 +212,7 @@ static int ellesmere_program_jump_on_start(struct pp_smumgr *smumgr)
*
* @param smumgr the address of the powerplay hardware manager.
*/
bool ellesmere_is_smc_ram_running(struct pp_smumgr *smumgr)
bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr)
{
return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
&& (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
@@ -225,9 +225,9 @@ bool ellesmere_is_smc_ram_running(struct pp_smumgr *smumgr)
* @param msg the message to send.
* @return The response that came from the SMC.
*/
int ellesmere_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
int polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
{
if (!ellesmere_is_smc_ram_running(smumgr))
if (!polaris10_is_smc_ram_running(smumgr))
return -1;
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
@@ -254,7 +254,7 @@ int ellesmere_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
* @param msg the message to send.
* @return Always return 0.
*/
int ellesmere_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg)
int polaris10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg)
{
cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
@@ -269,9 +269,9 @@ int ellesmere_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t
* @param parameter: the parameter to send
* @return The response that came from the SMC.
*/
int ellesmere_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
int polaris10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
{
if (!ellesmere_is_smc_ram_running(smumgr)) {
if (!polaris10_is_smc_ram_running(smumgr)) {
return -1;
}
@@ -279,7 +279,7 @@ int ellesmere_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
return ellesmere_send_msg_to_smc(smumgr, msg);
return polaris10_send_msg_to_smc(smumgr, msg);
}
@@ -291,14 +291,14 @@ int ellesmere_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t
* @param parameter: the parameter to send
* @return The response that came from the SMC.
*/
int ellesmere_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
int polaris10_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
{
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
return ellesmere_send_msg_to_smc_without_waiting(smumgr, msg);
return polaris10_send_msg_to_smc_without_waiting(smumgr, msg);
}
int ellesmere_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
int polaris10_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
{
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
@@ -319,10 +319,10 @@ int ellesmere_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
* @param msg the message to send.
* @return The response that came from the SMC.
*/
int ellesmere_wait_for_smc_inactive(struct pp_smumgr *smumgr)
int polaris10_wait_for_smc_inactive(struct pp_smumgr *smumgr)
{
/* If the SMC is not even on it qualifies as inactive. */
if (!ellesmere_is_smc_ram_running(smumgr))
if (!polaris10_is_smc_ram_running(smumgr))
return -1;
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
@@ -336,7 +336,7 @@ int ellesmere_wait_for_smc_inactive(struct pp_smumgr *smumgr)
* @param smumgr the address of the powerplay hardware manager.
* @param pFirmware the data structure containing the various sections of the firmware.
*/
static int ellesmere_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit)
static int polaris10_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit)
{
uint32_t byte_count = length;
@@ -355,7 +355,7 @@ static int ellesmere_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t
return 0;
}
static enum cgs_ucode_id ellesmere_convert_fw_type_to_cgs(uint32_t fw_type)
static enum cgs_ucode_id polaris10_convert_fw_type_to_cgs(uint32_t fw_type)
{
enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
@@ -400,22 +400,22 @@ static enum cgs_ucode_id ellesmere_convert_fw_type_to_cgs(uint32_t fw_type)
return result;
}
static int ellesmere_upload_smu_firmware_image(struct pp_smumgr *smumgr)
static int polaris10_upload_smu_firmware_image(struct pp_smumgr *smumgr)
{
int result = 0;
struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
struct cgs_firmware_info info = {0};
if (smu_data->security_hard_key == 1)
cgs_get_firmware_info(smumgr->device,
ellesmere_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
else
cgs_get_firmware_info(smumgr->device,
ellesmere_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
/* TO DO cgs_init_samu_load_smu(smumgr->device, (uint32_t *)info.kptr, info.image_size, smu_data->post_initial_boot);*/
result = ellesmere_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, ELLESMERE_SMC_SIZE);
result = polaris10_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, POLARIS10_SMC_SIZE);
return result;
}
@@ -427,11 +427,11 @@ static int ellesmere_upload_smu_firmware_image(struct pp_smumgr *smumgr)
* @param smcAddress the address in the SMC RAM to access.
* @param value and output parameter for the data read from the SMC SRAM.
*/
int ellesmere_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
{
int result;
result = ellesmere_set_smc_sram_address(smumgr, smc_addr, limit);
result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit);
if (result)
return result;
@@ -447,11 +447,11 @@ int ellesmere_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, u
* @param smc_addr the address in the SMC RAM to access.
* @param value to write to the SMC SRAM.
*/
int ellesmere_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
{
int result;
result = ellesmere_set_smc_sram_address(smumgr, smc_addr, limit);
result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit);
if (result)
return result;
@@ -462,7 +462,7 @@ int ellesmere_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
}
int ellesmere_smu_fini(struct pp_smumgr *smumgr)
int polaris10_smu_fini(struct pp_smumgr *smumgr)
{
if (smumgr->backend) {
kfree(smumgr->backend);
@@ -472,7 +472,7 @@ int ellesmere_smu_fini(struct pp_smumgr *smumgr)
}
/* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */
static uint32_t ellesmere_get_mask_for_firmware_type(uint32_t fw_type)
static uint32_t polaris10_get_mask_for_firmware_type(uint32_t fw_type)
{
uint32_t result = 0;
@@ -509,7 +509,7 @@ static uint32_t ellesmere_get_mask_for_firmware_type(uint32_t fw_type)
/* Populate one firmware image to the data structure */
static int ellesmere_populate_single_firmware_entry(struct pp_smumgr *smumgr,
static int polaris10_populate_single_firmware_entry(struct pp_smumgr *smumgr,
uint32_t fw_type,
struct SMU_Entry *entry)
{
@@ -517,7 +517,7 @@ static int ellesmere_populate_single_firmware_entry(struct pp_smumgr *smumgr,
struct cgs_firmware_info info = {0};
result = cgs_get_firmware_info(smumgr->device,
ellesmere_convert_fw_type_to_cgs(fw_type),
polaris10_convert_fw_type_to_cgs(fw_type),
&info);
if (!result) {
@@ -539,9 +539,9 @@ static int ellesmere_populate_single_firmware_entry(struct pp_smumgr *smumgr,
return 0;
}
static int ellesmere_request_smu_load_fw(struct pp_smumgr *smumgr)
static int polaris10_request_smu_load_fw(struct pp_smumgr *smumgr)
{
struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
uint32_t fw_to_load;
int result = 0;
@@ -557,25 +557,25 @@ static int ellesmere_request_smu_load_fw(struct pp_smumgr *smumgr)
smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus),
0x0);
ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high);
ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low);
polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high);
polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low);
toc = (struct SMU_DRAMData_TOC *)smu_data->header;
toc->num_entries = 0;
toc->structure_version = 1;
PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1);
ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
fw_to_load = UCODE_ID_RLC_G_MASK
+ UCODE_ID_SDMA0_MASK
@@ -585,17 +585,17 @@ static int ellesmere_request_smu_load_fw(struct pp_smumgr *smumgr)
+ UCODE_ID_CP_PFP_MASK
+ UCODE_ID_CP_MEC_MASK;
if (ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
if (polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
printk(KERN_ERR "Fail to Request SMU Load uCode");
return result;
}
/* Check if the FW has been loaded, SMU will not return if loading has not finished. */
static int ellesmere_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type)
static int polaris10_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type)
{
struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
uint32_t fw_mask = ellesmere_get_mask_for_firmware_type(fw_type);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
uint32_t fw_mask = polaris10_get_mask_for_firmware_type(fw_type);
uint32_t ret;
/* Check SOFT_REGISTERS_TABLE_28.UcodeLoadStatus */
ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11,
@@ -605,19 +605,19 @@ static int ellesmere_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_
return ret;
}
static int ellesmere_reload_firmware(struct pp_smumgr *smumgr)
static int polaris10_reload_firmware(struct pp_smumgr *smumgr)
{
return smumgr->smumgr_funcs->start_smu(smumgr);
}
static int ellesmere_setup_pwr_virus(struct pp_smumgr *smumgr)
static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
{
int i;
int result = -1;
uint32_t reg, data;
PWR_Command_Table *pvirus = pwr_virus_table;
struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
@@ -644,14 +644,14 @@ static int ellesmere_setup_pwr_virus(struct pp_smumgr *smumgr)
return result;
}
static int ellesmere_perform_btc(struct pp_smumgr *smumgr)
static int polaris10_perform_btc(struct pp_smumgr *smumgr)
{
int result = 0;
struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
if (0 != smu_data->avfs.avfs_btc_param) {
if (0 != ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
printk("[AVFS][SmuEllesmere_PerformBtc] PerformBTC SMU msg failed");
if (0 != polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
printk("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
result = -1;
}
}
@@ -667,7 +667,7 @@ static int ellesmere_perform_btc(struct pp_smumgr *smumgr)
}
int ellesmere_setup_graphics_level_structure(struct pp_smumgr *smumgr)
int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
{
uint32_t vr_config;
uint32_t dpm_table_start;
@@ -675,13 +675,13 @@ int ellesmere_setup_graphics_level_structure(struct pp_smumgr *smumgr)
uint16_t u16_boot_mvdd;
uint32_t graphics_level_address, vr_config_address, graphics_level_size;
graphics_level_size = sizeof(avfs_graphics_level_ellesmere);
graphics_level_size = sizeof(avfs_graphics_level_polaris10);
u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
PP_ASSERT_WITH_CODE(0 == ellesmere_read_smc_sram_dword(smumgr,
PP_ASSERT_WITH_CODE(0 == polaris10_read_smc_sram_dword(smumgr,
SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
&dpm_table_start, 0x40000),
"[AVFS][Ellesmere_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
"[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
return -1);
/* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
@@ -689,41 +689,41 @@ int ellesmere_setup_graphics_level_structure(struct pp_smumgr *smumgr)
vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, vr_config_address,
PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, vr_config_address,
(uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
"[AVFS][Ellesmere_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
"[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
return -1);
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address,
(uint8_t *)(&avfs_graphics_level_ellesmere),
PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
(uint8_t *)(&avfs_graphics_level_polaris10),
graphics_level_size, 0x40000),
"[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
return -1);
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address,
(uint8_t *)(&avfs_memory_level_ellesmere), sizeof(avfs_memory_level_ellesmere), 0x40000),
"[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
(uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
return -1);
/* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address,
PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address,
(uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
"[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of DPM table failed!",
"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
return -1);
return 0;
}
int ellesmere_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
{
struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
switch (smu_data->avfs.avfs_btc_status) {
case AVFS_BTC_COMPLETED_PREVIOUSLY:
@@ -732,21 +732,21 @@ int ellesmere_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
PP_ASSERT_WITH_CODE(0 == ellesmere_setup_graphics_level_structure(smumgr),
"[AVFS][Ellesmere_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(smumgr),
"[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
return -1);
if (smu_data->avfs.avfs_btc_param > 1) {
printk("[AVFS][Ellesmere_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
printk("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
PP_ASSERT_WITH_CODE(-1 == ellesmere_setup_pwr_virus(smumgr),
"[AVFS][Ellesmere_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
PP_ASSERT_WITH_CODE(-1 == polaris10_setup_pwr_virus(smumgr),
"[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
return -1);
}
smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
PP_ASSERT_WITH_CODE(0 == ellesmere_perform_btc(smumgr),
"[AVFS][Ellesmere_AVFSEventMgr] Failure at SmuEllesmere_PerformBTC. AVFS Disabled",
PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(smumgr),
"[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
return -1);
break;
@@ -763,7 +763,7 @@ int ellesmere_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
return 0;
}
static int ellesmere_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
{
int result = 0;
@@ -774,7 +774,7 @@ static int ellesmere_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
result = ellesmere_upload_smu_firmware_image(smumgr);
result = polaris10_upload_smu_firmware_image(smumgr);
if (result != 0)
return result;
@@ -793,7 +793,7 @@ static int ellesmere_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
/* Call Test SMU message with 0x20000 offset to trigger SMU start */
ellesmere_send_msg_to_smc_offset(smumgr);
polaris10_send_msg_to_smc_offset(smumgr);
/* Wait done bit to be set */
/* Check pass/failed indicator */
@@ -818,7 +818,7 @@ static int ellesmere_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
return result;
}
static int ellesmere_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
{
int result = 0;
@@ -834,12 +834,12 @@ static int ellesmere_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
SMC_SYSCON_RESET_CNTL,
rst_reg, 1);
result = ellesmere_upload_smu_firmware_image(smumgr);
result = polaris10_upload_smu_firmware_image(smumgr);
if (result != 0)
return result;
/* Set smc instruct start point at 0x0 */
ellesmere_program_jump_on_start(smumgr);
polaris10_program_jump_on_start(smumgr);
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
@@ -855,56 +855,56 @@ static int ellesmere_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
return result;
}
static int ellesmere_start_smu(struct pp_smumgr *smumgr)
static int polaris10_start_smu(struct pp_smumgr *smumgr)
{
int result = 0;
struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
bool SMU_VFT_INTACT;
/* Only start SMC if SMC RAM is not running */
if (!ellesmere_is_smc_ram_running(smumgr)) {
if (!polaris10_is_smc_ram_running(smumgr)) {
SMU_VFT_INTACT = false;
smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
smu_data->security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
/* Check if SMU is running in protected mode */
if (smu_data->protected_mode == 0) {
result = ellesmere_start_smu_in_non_protection_mode(smumgr);
result = polaris10_start_smu_in_non_protection_mode(smumgr);
} else {
result = ellesmere_start_smu_in_protection_mode(smumgr);
result = polaris10_start_smu_in_protection_mode(smumgr);
/* If failed, try with different security Key. */
if (result != 0) {
smu_data->security_hard_key ^= 1;
result = ellesmere_start_smu_in_protection_mode(smumgr);
result = polaris10_start_smu_in_protection_mode(smumgr);
}
}
if (result != 0)
PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
ellesmere_avfs_event_mgr(smumgr, true);
polaris10_avfs_event_mgr(smumgr, true);
} else
SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
smu_data->post_initial_boot = true;
ellesmere_avfs_event_mgr(smumgr, SMU_VFT_INTACT);
polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT);
/* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
ellesmere_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
polaris10_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
&(smu_data->soft_regs_start), 0x40000);
result = ellesmere_request_smu_load_fw(smumgr);
result = polaris10_request_smu_load_fw(smumgr);
return result;
}
static int ellesmere_smu_init(struct pp_smumgr *smumgr)
static int polaris10_smu_init(struct pp_smumgr *smumgr)
{
struct ellesmere_smumgr *smu_data;
struct polaris10_smumgr *smu_data;
uint8_t *internal_buf;
uint64_t mc_addr = 0;
/* Allocate memory for backend private data */
smu_data = (struct ellesmere_smumgr *)(smumgr->backend);
smu_data = (struct polaris10_smumgr *)(smumgr->backend);
smu_data->header_buffer.data_size =
((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
smu_data->smu_buffer.data_size = 200*4096;
@@ -955,28 +955,28 @@ static int ellesmere_smu_init(struct pp_smumgr *smumgr)
}
static const struct pp_smumgr_func ellsemere_smu_funcs = {
.smu_init = ellesmere_smu_init,
.smu_fini = ellesmere_smu_fini,
.start_smu = ellesmere_start_smu,
.check_fw_load_finish = ellesmere_check_fw_load_finish,
.request_smu_load_fw = ellesmere_reload_firmware,
.smu_init = polaris10_smu_init,
.smu_fini = polaris10_smu_fini,
.start_smu = polaris10_start_smu,
.check_fw_load_finish = polaris10_check_fw_load_finish,
.request_smu_load_fw = polaris10_reload_firmware,
.request_smu_load_specific_fw = NULL,
.send_msg_to_smc = ellesmere_send_msg_to_smc,
.send_msg_to_smc_with_parameter = ellesmere_send_msg_to_smc_with_parameter,
.send_msg_to_smc = polaris10_send_msg_to_smc,
.send_msg_to_smc_with_parameter = polaris10_send_msg_to_smc_with_parameter,
.download_pptable_settings = NULL,
.upload_pptable_settings = NULL,
};
int ellesmere_smum_init(struct pp_smumgr *smumgr)
int polaris10_smum_init(struct pp_smumgr *smumgr)
{
struct ellesmere_smumgr *ellesmere_smu = NULL;
struct polaris10_smumgr *polaris10_smu = NULL;
ellesmere_smu = kzalloc(sizeof(struct ellesmere_smumgr), GFP_KERNEL);
polaris10_smu = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
if (ellesmere_smu == NULL)
if (polaris10_smu == NULL)
return -1;
smumgr->backend = ellesmere_smu;
smumgr->backend = polaris10_smu;
smumgr->smumgr_funcs = &ellsemere_smu_funcs;
return 0;

26
drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h → drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h
Просмотреть файл

@@ -21,18 +21,18 @@
*
*/
#ifndef _ELLESMERE_SMUMANAGER_H
#define _ELLESMERE_SMUMANAGER_H
#ifndef _POLARIS10_SMUMANAGER_H
#define _POLARIS10_SMUMANAGER_H
#include <ellesmere_ppsmc.h>
#include <polaris10_ppsmc.h>
#include <pp_endian.h>
struct ellesmere_avfs {
struct polaris10_avfs {
enum AVFS_BTC_STATUS avfs_btc_status;
uint32_t avfs_btc_param;
};
struct ellesmere_buffer_entry {
struct polaris10_buffer_entry {
uint32_t data_size;
uint32_t mc_addr_low;
uint32_t mc_addr_high;
@@ -40,11 +40,11 @@ struct ellesmere_buffer_entry {
unsigned long handle;
};
struct ellesmere_smumgr {
struct polaris10_smumgr {
uint8_t *header;
uint8_t *mec_image;
struct ellesmere_buffer_entry smu_buffer;
struct ellesmere_buffer_entry header_buffer;
struct polaris10_buffer_entry smu_buffer;
struct polaris10_buffer_entry header_buffer;
uint32_t soft_regs_start;
uint8_t *read_rrm_straps;
uint32_t read_drm_straps_mc_address_high;
@@ -53,15 +53,15 @@ struct ellesmere_smumgr {
bool post_initial_boot;
uint8_t protected_mode;
uint8_t security_hard_key;
struct ellesmere_avfs avfs;
struct polaris10_avfs avfs;
};
int ellesmere_smum_init(struct pp_smumgr *smumgr);
int polaris10_smum_init(struct pp_smumgr *smumgr);
int ellesmere_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit);
int ellesmere_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit);
int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit);
int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit);
int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
const uint8_t *src, uint32_t byte_count, uint32_t limit);
#endif

8
drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
Просмотреть файл

@@ -30,7 +30,7 @@
#include "cz_smumgr.h"
#include "tonga_smumgr.h"
#include "fiji_smumgr.h"
#include "ellesmere_smumgr.h"
#include "polaris10_smumgr.h"
int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
{
@@ -63,9 +63,9 @@ int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
case CHIP_FIJI:
fiji_smum_init(smumgr);
break;
case CHIP_BAFFIN:
case CHIP_ELLESMERE:
ellesmere_smum_init(smumgr);
case CHIP_POLARIS11:
case CHIP_POLARIS10:
polaris10_smum_init(smumgr);
break;
default:
return -EINVAL;