clk: zynq: Use clk_readl/clk_writel helper function
Do not use readl/writel directly because the whole clk subsystem is using clk_readl/clk_writel functions. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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committed by
Mike Turquette

parent
95aa4f9b5f
commit
2c97ec5842
@@ -148,7 +148,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
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clks[fclk] = clk_register_gate(NULL, clk_name,
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clks[fclk] = clk_register_gate(NULL, clk_name,
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div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
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div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
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0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
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0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
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enable_reg = readl(fclk_gate_reg) & 1;
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enable_reg = clk_readl(fclk_gate_reg) & 1;
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if (enable && !enable_reg) {
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if (enable && !enable_reg) {
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if (clk_prepare_enable(clks[fclk]))
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if (clk_prepare_enable(clks[fclk]))
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pr_warn("%s: FCLK%u enable failed\n", __func__,
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pr_warn("%s: FCLK%u enable failed\n", __func__,
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@@ -277,7 +277,7 @@ static void __init zynq_clk_setup(struct device_node *np)
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SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
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SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
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/* CPU clocks */
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/* CPU clocks */
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tmp = readl(SLCR_621_TRUE) & 1;
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tmp = clk_readl(SLCR_621_TRUE) & 1;
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clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
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clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
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CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
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CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
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&armclk_lock);
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&armclk_lock);
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@@ -90,7 +90,7 @@ static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
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* makes probably sense to redundantly save fbdiv in the struct
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* makes probably sense to redundantly save fbdiv in the struct
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* zynq_pll to save the IO access.
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* zynq_pll to save the IO access.
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*/
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*/
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fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
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fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
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PLLCTRL_FBDIV_SHIFT;
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PLLCTRL_FBDIV_SHIFT;
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return parent_rate * fbdiv;
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return parent_rate * fbdiv;
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@@ -112,7 +112,7 @@ static int zynq_pll_is_enabled(struct clk_hw *hw)
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spin_lock_irqsave(clk->lock, flags);
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spin_lock_irqsave(clk->lock, flags);
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reg = readl(clk->pll_ctrl);
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reg = clk_readl(clk->pll_ctrl);
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spin_unlock_irqrestore(clk->lock, flags);
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spin_unlock_irqrestore(clk->lock, flags);
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@@ -138,10 +138,10 @@ static int zynq_pll_enable(struct clk_hw *hw)
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/* Power up PLL and wait for lock */
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/* Power up PLL and wait for lock */
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spin_lock_irqsave(clk->lock, flags);
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spin_lock_irqsave(clk->lock, flags);
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reg = readl(clk->pll_ctrl);
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reg = clk_readl(clk->pll_ctrl);
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reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
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reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
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writel(reg, clk->pll_ctrl);
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clk_writel(reg, clk->pll_ctrl);
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while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
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while (!(clk_readl(clk->pll_status) & (1 << clk->lockbit)))
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;
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;
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spin_unlock_irqrestore(clk->lock, flags);
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spin_unlock_irqrestore(clk->lock, flags);
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@@ -168,9 +168,9 @@ static void zynq_pll_disable(struct clk_hw *hw)
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/* shut down PLL */
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/* shut down PLL */
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spin_lock_irqsave(clk->lock, flags);
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spin_lock_irqsave(clk->lock, flags);
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reg = readl(clk->pll_ctrl);
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reg = clk_readl(clk->pll_ctrl);
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reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
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reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
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writel(reg, clk->pll_ctrl);
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clk_writel(reg, clk->pll_ctrl);
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spin_unlock_irqrestore(clk->lock, flags);
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spin_unlock_irqrestore(clk->lock, flags);
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}
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}
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@@ -225,9 +225,9 @@ struct clk *clk_register_zynq_pll(const char *name, const char *parent,
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spin_lock_irqsave(pll->lock, flags);
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spin_lock_irqsave(pll->lock, flags);
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reg = readl(pll->pll_ctrl);
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reg = clk_readl(pll->pll_ctrl);
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reg &= ~PLLCTRL_BPQUAL_MASK;
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reg &= ~PLLCTRL_BPQUAL_MASK;
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writel(reg, pll->pll_ctrl);
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clk_writel(reg, pll->pll_ctrl);
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spin_unlock_irqrestore(pll->lock, flags);
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spin_unlock_irqrestore(pll->lock, flags);
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