drm/amdgpu: remove unused and mostly unimplemented CGS functions v2
Those functions are all unused and some not even implemented. v2: keep cgs_get_pci_resource, it is used by the ACP driver. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König
committed by
Alex Deucher
Alex Deucher
parent
00c4855ef8
commit
2c55b16bf0
@@ -42,82 +42,6 @@ struct amdgpu_cgs_device {
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struct amdgpu_device *adev = \
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((struct amdgpu_cgs_device *)cgs_device)->adev
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static int amdgpu_cgs_gpu_mem_info(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
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uint64_t *mc_start, uint64_t *mc_size,
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uint64_t *mem_size)
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{
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CGS_FUNC_ADEV;
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switch(type) {
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case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
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case CGS_GPU_MEM_TYPE__VISIBLE_FB:
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*mc_start = 0;
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*mc_size = adev->mc.visible_vram_size;
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*mem_size = adev->mc.visible_vram_size - adev->vram_pin_size;
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break;
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case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
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case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
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*mc_start = adev->mc.visible_vram_size;
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*mc_size = adev->mc.real_vram_size - adev->mc.visible_vram_size;
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*mem_size = *mc_size;
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break;
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case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
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case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
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*mc_start = adev->mc.gtt_start;
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*mc_size = adev->mc.gtt_size;
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*mem_size = adev->mc.gtt_size - adev->gart_pin_size;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int amdgpu_cgs_gmap_kmem(struct cgs_device *cgs_device, void *kmem,
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uint64_t size,
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uint64_t min_offset, uint64_t max_offset,
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cgs_handle_t *kmem_handle, uint64_t *mcaddr)
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{
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CGS_FUNC_ADEV;
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int ret;
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struct amdgpu_bo *bo;
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struct page *kmem_page = vmalloc_to_page(kmem);
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int npages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT;
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struct sg_table *sg = drm_prime_pages_to_sg(&kmem_page, npages);
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ret = amdgpu_bo_create(adev, size, PAGE_SIZE, false,
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AMDGPU_GEM_DOMAIN_GTT, 0, sg, NULL, &bo);
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if (ret)
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return ret;
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ret = amdgpu_bo_reserve(bo, true);
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if (unlikely(ret != 0))
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return ret;
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/* pin buffer into GTT */
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ret = amdgpu_bo_pin_restricted(bo, AMDGPU_GEM_DOMAIN_GTT,
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min_offset, max_offset, mcaddr);
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amdgpu_bo_unreserve(bo);
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*kmem_handle = (cgs_handle_t)bo;
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return ret;
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}
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static int amdgpu_cgs_gunmap_kmem(struct cgs_device *cgs_device, cgs_handle_t kmem_handle)
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{
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struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle;
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if (obj) {
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int r = amdgpu_bo_reserve(obj, true);
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if (likely(r == 0)) {
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amdgpu_bo_unpin(obj);
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amdgpu_bo_unreserve(obj);
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}
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amdgpu_bo_unref(&obj);
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}
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return 0;
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}
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static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
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enum cgs_gpu_mem_type type,
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uint64_t size, uint64_t align,
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@@ -349,62 +273,6 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
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WARN(1, "Invalid indirect register space");
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}
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static uint8_t amdgpu_cgs_read_pci_config_byte(struct cgs_device *cgs_device, unsigned addr)
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{
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CGS_FUNC_ADEV;
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uint8_t val;
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int ret = pci_read_config_byte(adev->pdev, addr, &val);
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if (WARN(ret, "pci_read_config_byte error"))
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return 0;
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return val;
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}
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static uint16_t amdgpu_cgs_read_pci_config_word(struct cgs_device *cgs_device, unsigned addr)
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{
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CGS_FUNC_ADEV;
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uint16_t val;
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int ret = pci_read_config_word(adev->pdev, addr, &val);
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if (WARN(ret, "pci_read_config_word error"))
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return 0;
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return val;
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}
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static uint32_t amdgpu_cgs_read_pci_config_dword(struct cgs_device *cgs_device,
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unsigned addr)
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{
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CGS_FUNC_ADEV;
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uint32_t val;
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int ret = pci_read_config_dword(adev->pdev, addr, &val);
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if (WARN(ret, "pci_read_config_dword error"))
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return 0;
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return val;
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}
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static void amdgpu_cgs_write_pci_config_byte(struct cgs_device *cgs_device, unsigned addr,
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uint8_t value)
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{
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CGS_FUNC_ADEV;
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int ret = pci_write_config_byte(adev->pdev, addr, value);
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WARN(ret, "pci_write_config_byte error");
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}
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static void amdgpu_cgs_write_pci_config_word(struct cgs_device *cgs_device, unsigned addr,
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uint16_t value)
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{
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CGS_FUNC_ADEV;
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int ret = pci_write_config_word(adev->pdev, addr, value);
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WARN(ret, "pci_write_config_word error");
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}
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static void amdgpu_cgs_write_pci_config_dword(struct cgs_device *cgs_device, unsigned addr,
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uint32_t value)
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{
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CGS_FUNC_ADEV;
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int ret = pci_write_config_dword(adev->pdev, addr, value);
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WARN(ret, "pci_write_config_dword error");
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}
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static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device,
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enum cgs_resource_type resource_type,
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uint64_t size,
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@@ -477,56 +345,6 @@ static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigne
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adev->mode_info.atom_context, table, args);
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}
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static int amdgpu_cgs_create_pm_request(struct cgs_device *cgs_device, cgs_handle_t *request)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_destroy_pm_request(struct cgs_device *cgs_device, cgs_handle_t request)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_set_pm_request(struct cgs_device *cgs_device, cgs_handle_t request,
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int active)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_pm_request_clock(struct cgs_device *cgs_device, cgs_handle_t request,
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enum cgs_clock clock, unsigned freq)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_pm_request_engine(struct cgs_device *cgs_device, cgs_handle_t request,
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enum cgs_engine engine, int powered)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_pm_query_clock_limits(struct cgs_device *cgs_device,
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enum cgs_clock clock,
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struct cgs_clock_limits *limits)
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{
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/* TODO */
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return 0;
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}
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static int amdgpu_cgs_set_camera_voltages(struct cgs_device *cgs_device, uint32_t mask,
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const uint32_t *voltages)
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{
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DRM_ERROR("not implemented");
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return -EPERM;
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}
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struct cgs_irq_params {
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unsigned src_id;
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cgs_irq_source_set_func_t set;
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@@ -1269,9 +1087,6 @@ static int amdgpu_cgs_call_acpi_method(struct cgs_device *cgs_device,
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}
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static const struct cgs_ops amdgpu_cgs_ops = {
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.gpu_mem_info = amdgpu_cgs_gpu_mem_info,
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.gmap_kmem = amdgpu_cgs_gmap_kmem,
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.gunmap_kmem = amdgpu_cgs_gunmap_kmem,
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.alloc_gpu_mem = amdgpu_cgs_alloc_gpu_mem,
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.free_gpu_mem = amdgpu_cgs_free_gpu_mem,
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.gmap_gpu_mem = amdgpu_cgs_gmap_gpu_mem,
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@@ -1282,23 +1097,10 @@ static const struct cgs_ops amdgpu_cgs_ops = {
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.write_register = amdgpu_cgs_write_register,
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.read_ind_register = amdgpu_cgs_read_ind_register,
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.write_ind_register = amdgpu_cgs_write_ind_register,
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.read_pci_config_byte = amdgpu_cgs_read_pci_config_byte,
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.read_pci_config_word = amdgpu_cgs_read_pci_config_word,
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.read_pci_config_dword = amdgpu_cgs_read_pci_config_dword,
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.write_pci_config_byte = amdgpu_cgs_write_pci_config_byte,
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.write_pci_config_word = amdgpu_cgs_write_pci_config_word,
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.write_pci_config_dword = amdgpu_cgs_write_pci_config_dword,
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.get_pci_resource = amdgpu_cgs_get_pci_resource,
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.atom_get_data_table = amdgpu_cgs_atom_get_data_table,
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.atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs,
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.atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table,
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.create_pm_request = amdgpu_cgs_create_pm_request,
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.destroy_pm_request = amdgpu_cgs_destroy_pm_request,
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.set_pm_request = amdgpu_cgs_set_pm_request,
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.pm_request_clock = amdgpu_cgs_pm_request_clock,
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.pm_request_engine = amdgpu_cgs_pm_request_engine,
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.pm_query_clock_limits = amdgpu_cgs_pm_query_clock_limits,
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.set_camera_voltages = amdgpu_cgs_set_camera_voltages,
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.get_firmware_info = amdgpu_cgs_get_firmware_info,
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.rel_firmware = amdgpu_cgs_rel_firmware,
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.set_powergating_state = amdgpu_cgs_set_powergating_state,
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