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clk: rockchip: Fix PLL bandwidth

Bladeren bron 
In the TRM we see that BWADJ is "a 12-bit bus that selects the values
1-4096 for the bandwidth divider (NB)":
 NB = BWADJ[11:0] + 1
The recommended setting of NB: NB = NF / 2.

So:
  NB = NF / 2
  BWADJ[11:0] + 1 = NF / 2
  BWADJ[11:0] = NF / 2 - 1

Right now, we have:

{                                               \
        .rate   = _rate##U,                     \
        .nr = _nr,                              \
        .nf = _nf,                              \
        .no = _no,                              \
        .bwadj = (_nf >> 1),                    \
}

That means we set bwadj to NF / 2, not NF / 2 - 1

All of this is a bit confusing because we specify "NR" (the 1-based
value), "NF" (the 1-based value), "NO" (the 1-based value), but
"BWADJ" (the 0-based value) instead of "NB" (the 1-based value).

Let's change to working with "NB" and fix the off by one error.  This
may affect PLL jitter in a small way (hopefully for the better).

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Douglas Anderson
2015-07-21 13:41:23 -07:00
gecommit door Stephen Boyd
bovenliggende 9cfad9bc47
commit 2bbfe00147
4 gewijzigde bestanden met toevoegingen van 15 en 15 verwijderingen
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8
drivers/clk/rockchip/clk.h
Bestand weergeven

@@ -83,16 +83,16 @@ enum rockchip_pll_type {
.nr = _nr, \
.nf = _nf, \
.no = _no, \
.bwadj = ((_nf) >> 1), \
.nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
}
#define RK3066_PLL_RATE_BWADJ(_rate, _nr, _nf, _no, _bw) \
#define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
{ \
.rate = _rate##U, \
.nr = _nr, \
.nf = _nf, \
.no = _no, \
.bwadj = _bw, \
.nb = _nb, \
}
struct rockchip_pll_rate_table {
@@ -100,7 +100,7 @@ struct rockchip_pll_rate_table {
unsigned int nr;
unsigned int nf;
unsigned int no;
unsigned int bwadj;
unsigned int nb;
};
/**