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x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface

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The patch adds CHT PMC interface. This exposes all the South IP
device power states and S0ix states for CHT. The bit map of
FUNC_DIS and D3_STS_0 registers for SoCs are consistent. The
D3_STS_1 and FUNC_DIS_2 registers, however, are not aligned.
This is fixed by splitting a common mapping on per register basis.

(Originally based on code from Kumar P Mahesh.)

Originally-from: Kumar P Mahesh <mahesh.kumar.p@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Aubrey Li <aubrey.li@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1436192944-56496-5-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Andy Shevchenko
2015-07-06 17:29:03 +03:00
committed by Ingo Molnar
parent 940406d1cf
commit 2b8f8eddaf
2 changed files with 114 additions and 29 deletions
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25
arch/x86/include/asm/pmc_atom.h
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@@ -18,6 +18,8 @@
/* ValleyView Power Control Unit PCI Device ID */
#define PCI_DEVICE_ID_VLV_PMC 0x0F1C
/* CherryTrail Power Control Unit PCI Device ID */
#define PCI_DEVICE_ID_CHT_PMC 0x229C
/* PMC Memory mapped IO registers */
#define PMC_BASE_ADDR_OFFSET 0x44
@@ -29,6 +31,10 @@
#define PMC_FUNC_DIS 0x34
#define PMC_FUNC_DIS_2 0x38
/* CHT specific bits in FUNC_DIS2 register */
#define BIT_FD_GMM BIT(3)
#define BIT_FD_ISH BIT(4)
/* S0ix wake event control */
#define PMC_S0IX_WAKE_EN 0x3C
@@ -75,6 +81,21 @@
#define PMC_PSS_BIT_USB BIT(16)
#define PMC_PSS_BIT_USB_SUS BIT(17)
/* CHT specific bits in PSS register */
#define PMC_PSS_BIT_CHT_UFS BIT(7)
#define PMC_PSS_BIT_CHT_UXD BIT(11)
#define PMC_PSS_BIT_CHT_UXD_FD BIT(12)
#define PMC_PSS_BIT_CHT_UX_ENG BIT(15)
#define PMC_PSS_BIT_CHT_USB_SUS BIT(16)
#define PMC_PSS_BIT_CHT_GMM BIT(17)
#define PMC_PSS_BIT_CHT_ISH BIT(18)
#define PMC_PSS_BIT_CHT_DFX_MASTER BIT(26)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER1 BIT(27)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER2 BIT(28)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER3 BIT(29)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER4 BIT(30)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER5 BIT(31)
/* These registers reflect D3 status of functions */
#define PMC_D3_STS_0 0xA0
@@ -117,6 +138,10 @@
#define BIT_USH_SS_PHY BIT(2)
#define BIT_DFX BIT(3)
/* CHT specific bits in PMC_D3_STS_1 register */
#define BIT_STS_GMM BIT(1)
#define BIT_STS_ISH BIT(2)
/* PMC I/O Registers */
#define ACPI_BASE_ADDR_OFFSET 0x40
#define ACPI_BASE_ADDR_MASK 0xFFFFFE00