ARM: dts: stm32: use right pinctrl compatible for stm32f469
Currently, same stm32f429-pinctrl driver is used for stm32f429 and
stm32f469. As pin map is different between those 2 MCUs,
a stm32f469-pinctrl driver has been recently added.
This patch
-allows to use stm32f469-pinctrl driver for stm32f469 boards
-reworks stm32 devicetree files to fit with stm32f429 / stm32f469
In the same time it fixes an issue when only MACH_STM32F469 flag is
selected in menuconfig.
Fixes: d28bcd53fa ("ARM: stm32: Introduce MACH_STM32F469 flag")
Reported-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This commit is contained in:
Alexandre Torgue
@@ -47,7 +47,6 @@
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#include "skeleton.dtsi"
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#include "armv7-m.dtsi"
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#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
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#include <dt-bindings/clock/stm32fx-clock.h>
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#include <dt-bindings/mfd/stm32f4-rcc.h>
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@@ -591,302 +590,6 @@
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status = "disabled";
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};
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pinctrl: pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32f429-pinctrl";
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ranges = <0 0x40020000 0x3000>;
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interrupt-parent = <&exti>;
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st,syscfg = <&syscfg 0x8>;
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pins-are-numbered;
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gpioa: gpio@40020000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
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st,bank-name = "GPIOA";
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};
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gpiob: gpio@40020400 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x400 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
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st,bank-name = "GPIOB";
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};
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gpioc: gpio@40020800 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x800 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
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st,bank-name = "GPIOC";
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};
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gpiod: gpio@40020c00 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xc00 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
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st,bank-name = "GPIOD";
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};
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gpioe: gpio@40021000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
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st,bank-name = "GPIOE";
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};
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gpiof: gpio@40021400 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1400 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
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st,bank-name = "GPIOF";
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};
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gpiog: gpio@40021800 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1800 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
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st,bank-name = "GPIOG";
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};
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gpioh: gpio@40021c00 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1c00 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
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st,bank-name = "GPIOH";
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};
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gpioi: gpio@40022000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
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st,bank-name = "GPIOI";
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};
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gpioj: gpio@40022400 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2400 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
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st,bank-name = "GPIOJ";
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};
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gpiok: gpio@40022800 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2800 0x400>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
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st,bank-name = "GPIOK";
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};
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usart1_pins_a: usart1@0 {
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pins1 {
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pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
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bias-disable;
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};
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};
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usart3_pins_a: usart3@0 {
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pins1 {
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pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
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bias-disable;
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};
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};
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usbotg_fs_pins_a: usbotg_fs@0 {
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pins {
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pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
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<STM32F429_PA11_FUNC_OTG_FS_DM>,
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<STM32F429_PA12_FUNC_OTG_FS_DP>;
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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usbotg_fs_pins_b: usbotg_fs@1 {
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pins {
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pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
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<STM32F429_PB14_FUNC_OTG_HS_DM>,
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<STM32F429_PB15_FUNC_OTG_HS_DP>;
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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usbotg_hs_pins_a: usbotg_hs@0 {
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pins {
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pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
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<STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
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<STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
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<STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
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<STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
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<STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
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<STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
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<STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
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<STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
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<STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
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<STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
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<STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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ethernet_mii: mii@0 {
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pins {
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pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
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<STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
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<STM32F429_PC2_FUNC_ETH_MII_TXD2>,
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<STM32F429_PB8_FUNC_ETH_MII_TXD3>,
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<STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
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<STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
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<STM32F429_PA2_FUNC_ETH_MDIO>,
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<STM32F429_PC1_FUNC_ETH_MDC>,
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<STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
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<STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
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<STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
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<STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
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<STM32F429_PH6_FUNC_ETH_MII_RXD2>,
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<STM32F429_PH7_FUNC_ETH_MII_RXD3>;
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slew-rate = <2>;
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};
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};
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adc3_in8_pin: adc@200 {
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pins {
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pinmux = <STM32F429_PF10_FUNC_ANALOG>;
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};
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};
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pwm1_pins: pwm@1 {
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pins {
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pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
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<STM32F429_PB13_FUNC_TIM1_CH1N>,
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<STM32F429_PB12_FUNC_TIM1_BKIN>;
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};
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};
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pwm3_pins: pwm@3 {
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pins {
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pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
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<STM32F429_PB5_FUNC_TIM3_CH2>;
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};
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};
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i2c1_pins: i2c1@0 {
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pins {
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pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
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<STM32F429_PB6_FUNC_I2C1_SCL>;
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bias-disable;
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drive-open-drain;
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slew-rate = <3>;
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};
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};
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ltdc_pins: ltdc@0 {
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pins {
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pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
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<STM32F429_PI13_FUNC_LCD_VSYNC>,
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<STM32F429_PI14_FUNC_LCD_CLK>,
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<STM32F429_PI15_FUNC_LCD_R0>,
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<STM32F429_PJ0_FUNC_LCD_R1>,
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<STM32F429_PJ1_FUNC_LCD_R2>,
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<STM32F429_PJ2_FUNC_LCD_R3>,
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<STM32F429_PJ3_FUNC_LCD_R4>,
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<STM32F429_PJ4_FUNC_LCD_R5>,
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<STM32F429_PJ5_FUNC_LCD_R6>,
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<STM32F429_PJ6_FUNC_LCD_R7>,
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<STM32F429_PJ7_FUNC_LCD_G0>,
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<STM32F429_PJ8_FUNC_LCD_G1>,
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<STM32F429_PJ9_FUNC_LCD_G2>,
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<STM32F429_PJ10_FUNC_LCD_G3>,
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<STM32F429_PJ11_FUNC_LCD_G4>,
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<STM32F429_PJ12_FUNC_LCD_B0>,
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<STM32F429_PJ13_FUNC_LCD_B1>,
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<STM32F429_PJ14_FUNC_LCD_B2>,
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<STM32F429_PJ15_FUNC_LCD_B3>,
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<STM32F429_PK0_FUNC_LCD_G5>,
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<STM32F429_PK1_FUNC_LCD_G6>,
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<STM32F429_PK2_FUNC_LCD_G7>,
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<STM32F429_PK3_FUNC_LCD_B4>,
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<STM32F429_PK4_FUNC_LCD_B5>,
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<STM32F429_PK5_FUNC_LCD_B6>,
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<STM32F429_PK6_FUNC_LCD_B7>,
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<STM32F429_PK7_FUNC_LCD_DE>;
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slew-rate = <2>;
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};
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};
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dcmi_pins: dcmi@0 {
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pins {
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pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>,
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<STM32F429_PB7_FUNC_DCMI_VSYNC>,
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<STM32F429_PA6_FUNC_DCMI_PIXCLK>,
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<STM32F429_PC6_FUNC_DCMI_D0>,
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<STM32F429_PC7_FUNC_DCMI_D1>,
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<STM32F429_PC8_FUNC_DCMI_D2>,
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<STM32F429_PC9_FUNC_DCMI_D3>,
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<STM32F429_PC11_FUNC_DCMI_D4>,
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<STM32F429_PD3_FUNC_DCMI_D5>,
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<STM32F429_PB8_FUNC_DCMI_D6>,
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<STM32F429_PE6_FUNC_DCMI_D7>,
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<STM32F429_PC10_FUNC_DCMI_D8>,
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<STM32F429_PC12_FUNC_DCMI_D9>,
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<STM32F429_PD6_FUNC_DCMI_D10>,
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<STM32F429_PD2_FUNC_DCMI_D11>;
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bias-disable;
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drive-push-pull;
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slew-rate = <3>;
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};
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};
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};
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crc: crc@40023000 {
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compatible = "st,stm32f4-crc";
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reg = <0x40023000 0x400>;
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