sh: Solution Engine SH7705 board and CPU updates.
This fixes up SH7705 CPU support and the SE7705 board for some of the recent changes. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Nobuhiro Iwamatsu
committed by
Paul Mundt
Paul Mundt
parent
005a336e71
commit
2a8ff4596c
@@ -4,6 +4,6 @@
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obj-y += imask.o
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obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o
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obj-$(CONFIG_CPU_HAS_PINT_IRQ) += pint.o
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obj-$(CONFIG_CPU_HAS_PINT_IRQ) += pint.o
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obj-$(CONFIG_CPU_HAS_MASKREG_IRQ) += maskreg.o
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obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o
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@@ -18,6 +18,58 @@
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#include <asm/io.h>
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#include <asm/machvec.h>
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#if defined(CONFIG_CPU_SUBTYPE_SH7705)
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#define INTC_INTER 0xA4000014UL
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#define INTC_IPRD 0xA4000018UL
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#define INTC_ICR2 0xA4000012UL
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/* PFC */
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#define PORT_PACR 0xA4000100UL
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#define PORT_PBCR 0xA4000102UL
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#define PORT_PCCR 0xA4000104UL
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#define PORT_PDCR 0xA4000106UL
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#define PORT_PECR 0xA4000108UL
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#define PORT_PFCR 0xA400010AUL
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#define PORT_PGCR 0xA400010CUL
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#define PORT_PHCR 0xA400010EUL
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#define PORT_PJCR 0xA4000110UL
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#define PORT_PKCR 0xA4000112UL
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#define PORT_PLCR 0xA4000114UL
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#define PORT_PMCR 0xA4000118UL
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#define PORT_PNCR 0xA400011AUL
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#define PORT_PECR2 0xA4050148UL
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#define PORT_PFCR2 0xA405014AUL
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#define PORT_PNCR2 0xA405015AUL
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/* I/O port */
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#define PORT_PADR 0xA4000120UL
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#define PORT_PBDR 0xA4000122UL
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#define PORT_PCDR 0xA4000124UL
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#define PORT_PDDR 0xA4000126UL
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#define PORT_PEDR 0xA4000128UL
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#define PORT_PFDR 0xA400012AUL
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#define PORT_PGDR 0xA400012CUL
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#define PORT_PHDR 0xA400012EUL
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#define PORT_PJDR 0xA4000130UL
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#define PORT_PKDR 0xA4000132UL
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#define PORT_PLDR 0xA4000134UL
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#define PORT_PMDR 0xA4000138UL
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#define PORT_PNDR 0xA400013AUL
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#define PINT0_IRQ 40
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#define PINT8_IRQ 41
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#define PINT_IRQ_BASE 86
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#define PINT0_IPR_ADDR INTC_IPRD
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#define PINT0_IPR_POS 3
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#define PINT0_PRIORITY 2
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#define PINT8_IPR_ADDR INTC_IPRD
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#define PINT8_IPR_POS 2
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#define PINT8_PRIORITY 2
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#endif /* CONFIG_CPU_SUBTYPE_SH7705 */
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static unsigned char pint_map[256];
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static unsigned long portcr_mask;
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@@ -126,7 +178,7 @@ int ipr_irq_demux(int irq)
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unsigned long creg, dreg, d, sav;
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if (irq == PINT0_IRQ) {
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#if defined(CONFIG_CPU_SUBTYPE_SH7707)
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7707)
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creg = PORT_PACR;
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dreg = PORT_PADR;
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#else
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@@ -144,7 +196,7 @@ int ipr_irq_demux(int irq)
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return PINT_IRQ_BASE + pint_map[d];
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} else if (irq == PINT8_IRQ) {
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#if defined(CONFIG_CPU_SUBTYPE_SH7707)
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7707)
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creg = PORT_PBCR;
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dreg = PORT_PBDR;
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#else
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@@ -2,6 +2,7 @@
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* SH7705 Setup
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*
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* Copyright (C) 2006 Paul Mundt
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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@@ -14,15 +15,15 @@
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xa4400000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 52, 53, 55, 54 },
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}, {
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.mapbase = 0xa4410000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 56, 57, 59, 58 },
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.irqs = { 56, 57, 59 },
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}, {
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.mapbase = 0xa4400000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 52, 53, 55 },
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}, {
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.flags = 0,
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}
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@@ -46,3 +47,48 @@ static int __init sh7705_devices_setup(void)
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ARRAY_SIZE(sh7705_devices));
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}
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__initcall(sh7705_devices_setup);
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static struct ipr_data sh7705_ipr_map[] = {
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/* IRQ, IPR-idx, shift, priority */
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{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
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{ 17, 0, 8, 2 }, /* TMU1 TUNI */
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{ 18, 0, 4, 2 }, /* TMU2 TUNI */
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{ 27, 1, 12, 2 }, /* WDT ITI */
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{ 20, 0, 0, 2 }, /* RTC ATI (alarm) */
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{ 21, 0, 0, 2 }, /* RTC PRI (period) */
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{ 22, 0, 0, 2 }, /* RTC CUI (carry) */
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{ 48, 4, 12, 7 }, /* DMAC DMTE0 */
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{ 49, 4, 12, 7 }, /* DMAC DMTE1 */
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{ 50, 4, 12, 7 }, /* DMAC DMTE2 */
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{ 51, 4, 12, 7 }, /* DMAC DMTE3 */
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{ 52, 4, 8, 3 }, /* SCIF0 ERI */
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{ 53, 4, 8, 3 }, /* SCIF0 RXI */
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{ 55, 4, 8, 3 }, /* SCIF0 TXI */
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{ 56, 4, 4, 3 }, /* SCIF1 ERI */
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{ 57, 4, 4, 3 }, /* SCIF1 RXI */
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{ 59, 4, 4, 3 }, /* SCIF1 TXI */
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};
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static unsigned long ipr_offsets[] = {
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0xFFFFFEE2 /* 0: IPRA */
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, 0xFFFFFEE4 /* 1: IPRB */
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, 0xA4000016 /* 2: IPRC */
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, 0xA4000018 /* 3: IPRD */
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, 0xA400001A /* 4: IPRE */
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, 0xA4080000 /* 5: IPRF */
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, 0xA4080002 /* 6: IPRG */
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, 0xA4080004 /* 7: IPRH */
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};
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/* given the IPR index return the address of the IPR register */
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unsigned int map_ipridx_to_addr(int idx)
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{
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if (idx >= ARRAY_SIZE(ipr_offsets))
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return 0;
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return ipr_offsets[idx];
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}
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void __init init_IRQ_ipr()
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{
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make_ipr_irq(sh7705_ipr_map, ARRAY_SIZE(sh7705_ipr_map));
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}
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