powerpc/mm: Split low level tlb invalidate for nohash processors
Currently, the various forms of low level TLB invalidations are all implemented in misc_32.S for 32-bit processors, in a fairly scary mess of #ifdef's and with interesting duplication such as a whole bunch of code for FSL _tlbie and _tlbia which are no longer used. This moves things around such that _tlbie is now defined in hash_low_32.S and is only used by the 32-bit hash code, and all nohash CPUs use the various _tlbil_* forms that are now moved to a new file, tlb_nohash_low.S. I moved all the definitions for that stuff out of include/asm/tlbflush.h as they are really internal mm stuff, into mm/mmu_decl.h The code should have no functional changes. I kept some variants inline for trivial forms on things like 40x and 8xx. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
zatwierdzone przez
Paul Mackerras
Paul Mackerras
rodzic
f048aace29
commit
2a4aca1144
@@ -272,239 +272,6 @@ _GLOBAL(real_writeb)
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#endif /* CONFIG_40x */
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/*
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* Flush MMU TLB
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*/
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#ifndef CONFIG_FSL_BOOKE
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_GLOBAL(_tlbil_all)
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_GLOBAL(_tlbil_pid)
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#endif
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_GLOBAL(_tlbia)
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#if defined(CONFIG_40x)
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sync /* Flush to memory before changing mapping */
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tlbia
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isync /* Flush shadow TLB */
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#elif defined(CONFIG_44x)
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li r3,0
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sync
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/* Load high watermark */
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lis r4,tlb_44x_hwater@ha
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lwz r5,tlb_44x_hwater@l(r4)
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1: tlbwe r3,r3,PPC44x_TLB_PAGEID
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addi r3,r3,1
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cmpw 0,r3,r5
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ble 1b
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isync
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#elif defined(CONFIG_FSL_BOOKE)
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/* Invalidate all entries in TLB0 */
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li r3, 0x04
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tlbivax 0,3
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/* Invalidate all entries in TLB1 */
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li r3, 0x0c
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tlbivax 0,3
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msync
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#ifdef CONFIG_SMP
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tlbsync
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#endif /* CONFIG_SMP */
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#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
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#if defined(CONFIG_SMP)
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rlwinm r8,r1,0,0,(31-THREAD_SHIFT)
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lwz r8,TI_CPU(r8)
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oris r8,r8,10
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mfmsr r10
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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SYNC_601
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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sync
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tlbia
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sync
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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SYNC_601
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isync
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#else /* CONFIG_SMP */
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sync
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tlbia
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sync
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#endif /* CONFIG_SMP */
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#endif /* ! defined(CONFIG_40x) */
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blr
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/*
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* Flush MMU TLB for a particular address
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*/
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#ifndef CONFIG_FSL_BOOKE
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_GLOBAL(_tlbil_va)
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#endif
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_GLOBAL(_tlbie)
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#if defined(CONFIG_40x)
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/* We run the search with interrupts disabled because we have to change
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* the PID and I don't want to preempt when that happens.
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*/
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mfmsr r5
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mfspr r6,SPRN_PID
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wrteei 0
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mtspr SPRN_PID,r4
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tlbsx. r3, 0, r3
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mtspr SPRN_PID,r6
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wrtee r5
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bne 10f
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sync
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/* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
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* Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
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* the TLB entry. */
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tlbwe r3, r3, TLB_TAG
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isync
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10:
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#elif defined(CONFIG_44x)
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mfspr r5,SPRN_MMUCR
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rlwimi r5,r4,0,24,31 /* Set TID */
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/* We have to run the search with interrupts disabled, even critical
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* and debug interrupts (in fact the only critical exceptions we have
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* are debug and machine check). Otherwise an interrupt which causes
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* a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
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mfmsr r4
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lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
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addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
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andc r6,r4,r6
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mtmsr r6
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mtspr SPRN_MMUCR,r5
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tlbsx. r3, 0, r3
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mtmsr r4
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bne 10f
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sync
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/* There are only 64 TLB entries, so r3 < 64,
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* which means bit 22, is clear. Since 22 is
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* the V bit in the TLB_PAGEID, loading this
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* value will invalidate the TLB entry.
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*/
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tlbwe r3, r3, PPC44x_TLB_PAGEID
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isync
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10:
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#elif defined(CONFIG_FSL_BOOKE)
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rlwinm r4, r3, 0, 0, 19
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ori r5, r4, 0x08 /* TLBSEL = 1 */
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tlbivax 0, r4
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tlbivax 0, r5
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msync
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#if defined(CONFIG_SMP)
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tlbsync
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#endif /* CONFIG_SMP */
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#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
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#if defined(CONFIG_SMP)
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rlwinm r8,r1,0,0,(31-THREAD_SHIFT)
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lwz r8,TI_CPU(r8)
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oris r8,r8,11
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mfmsr r10
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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SYNC_601
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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eieio
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tlbie r3
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sync
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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SYNC_601
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isync
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#else /* CONFIG_SMP */
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tlbie r3
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sync
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#endif /* CONFIG_SMP */
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#endif /* ! CONFIG_40x */
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blr
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#if defined(CONFIG_FSL_BOOKE)
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/*
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* Flush MMU TLB, but only on the local processor (no broadcast)
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*/
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_GLOBAL(_tlbil_all)
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#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
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MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
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li r3,(MMUCSR0_TLBFI)@l
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mtspr SPRN_MMUCSR0, r3
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1:
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mfspr r3,SPRN_MMUCSR0
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andi. r3,r3,MMUCSR0_TLBFI@l
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bne 1b
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blr
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/*
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* Flush MMU TLB for a particular process id, but only on the local processor
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* (no broadcast)
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*/
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_GLOBAL(_tlbil_pid)
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/* we currently do an invalidate all since we don't have per pid invalidate */
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li r3,(MMUCSR0_TLBFI)@l
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mtspr SPRN_MMUCSR0, r3
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1:
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mfspr r3,SPRN_MMUCSR0
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andi. r3,r3,MMUCSR0_TLBFI@l
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bne 1b
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msync
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isync
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blr
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/*
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* Flush MMU TLB for a particular address, but only on the local processor
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* (no broadcast)
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*/
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_GLOBAL(_tlbil_va)
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mfmsr r10
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wrteei 0
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slwi r4,r4,16
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mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
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tlbsx 0,r3
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mfspr r4,SPRN_MAS1 /* check valid */
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andis. r3,r4,MAS1_VALID@h
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beq 1f
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rlwinm r4,r4,0,1,31
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mtspr SPRN_MAS1,r4
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tlbwe
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msync
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isync
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1: wrtee r10
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blr
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#endif /* CONFIG_FSL_BOOKE */
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/*
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* Nobody implements this yet
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*/
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_GLOBAL(_tlbivax_bcast)
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1: trap
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EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
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blr
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/*
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* Flush instruction cache.
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