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MIPS: Netlogic: Move from u32 cpumask to cpumask_t

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Initial code to support more than 32 cpus. The platform CPU mask
is updated from 32-bit mask to cpumask_t. Convert places that use
cpu_/cpus_ functions to use cpumask_* functions.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4464
Signed-off-by: John Crispin <blogic@openwrt.org>
This commit is contained in:
Jayachandran C
2012-10-31 12:01:37 +00:00
committed by John Crispin
parent 7143246e9a
commit 2a37b1ae44
6 changed files with 86 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/mips/netlogic/xlp/setup.c
View File

@@ -55,7 +55,8 @@
unsigned long nlm_common_ebase = 0x0;
/* default to uniprocessor */
uint32_t nlm_coremask = 1, nlm_cpumask = 1;
uint32_t nlm_coremask = 1;
cpumask_t nlm_cpumask = CPU_MASK_CPU0;
int nlm_threads_per_core = 1;
extern u32 __dtb_start[];
@@ -115,7 +116,8 @@ void __init prom_init(void)
nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
#ifdef CONFIG_SMP
nlm_wakeup_secondary_cpus(0xffffffff);
cpumask_setall(&nlm_cpumask);
nlm_wakeup_secondary_cpus();
/* update TLB size after waking up threads */
current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;

77
arch/mips/netlogic/xlp/wakeup.c
View File

@@ -51,45 +51,66 @@
#include <asm/netlogic/xlp-hal/xlp.h>
#include <asm/netlogic/xlp-hal/sys.h>
static void xlp_enable_secondary_cores(void)
static int xlp_wakeup_core(uint64_t sysbase, int core)
{
uint32_t core, value, coremask, syscoremask;
uint32_t coremask, value;
int count;
/* read cores in reset from SYS block */
syscoremask = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
coremask = (1 << core);
/* update user specified */
nlm_coremask = nlm_coremask & (syscoremask | 1);
/* Enable CPU clock */
value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
value &= ~coremask;
nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
for (core = 1; core < 8; core++) {
coremask = 1 << core;
if ((nlm_coremask & coremask) == 0)
continue;
/* Remove CPU Reset */
value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
value &= ~coremask;
nlm_write_sys_reg(sysbase, SYS_CPU_RESET, value);
/* Enable CPU clock */
value = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL);
value &= ~coremask;
nlm_write_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL, value);
/* Poll for CPU to mark itself coherent */
count = 100000;
do {
value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
} while ((value & coremask) != 0 && --count > 0);
/* Remove CPU Reset */
value = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
value &= ~coremask;
nlm_write_sys_reg(nlm_sys_base, SYS_CPU_RESET, value);
return count != 0;
}
/* Poll for CPU to mark itself coherent */
count = 100000;
do {
value = nlm_read_sys_reg(nlm_sys_base,
SYS_CPU_NONCOHERENT_MODE);
} while ((value & coremask) != 0 && count-- > 0);
static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
{
uint64_t syspcibase, sysbase;
uint32_t syscoremask;
int core, n;
if (count == 0)
pr_err("Failed to enable core %d\n", core);
for (n = 0; n < 4; n++) {
syspcibase = nlm_get_sys_pcibase(n);
if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
break;
/* read cores in reset from SYS and account for boot cpu */
sysbase = nlm_get_sys_regbase(n);
syscoremask = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
if (n == 0)
syscoremask |= 1;
for (core = 0; core < 8; core++) {
/* see if the core exists */
if ((syscoremask & (1 << core)) == 0)
continue;
/* see if at least the first thread is enabled */
if (!cpumask_test_cpu((n * 8 + core) * 4, wakeup_mask))
continue;
/* wake up the core */
if (!xlp_wakeup_core(sysbase, core))
pr_err("Failed to enable core %d\n", core);
}
}
}
void xlp_wakeup_secondary_cpus(void)
void xlp_wakeup_secondary_cpus()
{
/*
* In case of u-boot, the secondaries are in reset
@@ -98,5 +119,5 @@ void xlp_wakeup_secondary_cpus(void)
xlp_boot_core0_siblings();
/* now get other cores out of reset */
xlp_enable_secondary_cores();
xlp_enable_secondary_cores(&nlm_cpumask);
}