Merge tag 'usb-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB updates from Greg KH: "Here's the big USB patchset for 4.2-rc1. As is normal these days, the majority of changes are in the gadget drivers, with a bunch of other small driver changes. All of these have been in linux-next with no reported issues" * tag 'usb-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (175 commits) usb: dwc3: Use ASCII space in Kconfig usb: chipidea: add work-around for Marvell HSIC PHY startup usb: chipidea: allow multiple instances to use default ci_default_pdata dt-bindings: Consolidate ChipIdea USB ci13xxx bindings phy: add Marvell HSIC 28nm PHY phy: Add Marvell USB 2.0 OTG 28nm PHY dt-bindings: Add Marvell PXA1928 USB and HSIC PHY bindings USB: ssb: use devm_kzalloc USB: ssb: fix error handling in ssb_hcd_create_pdev() usb: isp1760: check for null return from kzalloc cdc-acm: Add support of ATOL FPrint fiscal printers usb: chipidea: usbmisc_imx: Remove unneeded semicolon USB: usbtmc: add device quirk for Rigol DS6104 USB: serial: mos7840: Use setup_timer phy: twl4030-usb: add ABI documentation phy: twl4030-usb: remove incorrect pm_runtime_get_sync() in probe function. phy: twl4030-usb: remove pointless 'suspended' test in 'suspend' callback. phy: twl4030-usb: make runtime pm more reliable. drivers:usb:fsl: Fix compilation error for fsl ehci drv usb: renesas_usbhs: Don't disable the pipe if Control write status stage ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,40 @@
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* Broadcom SATA3 PHY for STB
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Required properties:
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- compatible: should be one or more of
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"brcm,bcm7445-sata-phy"
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"brcm,phy-sata3"
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- address-cells: should be 1
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- size-cells: should be 0
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- reg: register range for the PHY PCB interface
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- reg-names: should be "phy"
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Sub-nodes:
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Each port's PHY should be represented as a sub-node.
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Sub-nodes required properties:
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- reg: the PHY number
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- phy-cells: generic PHY binding; must be 0
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Optional:
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- brcm,enable-ssc: use spread spectrum clocking (SSC) on this port
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Example:
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sata-phy@f0458100 {
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compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
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reg = <0xf0458100 0x1e00>, <0xf045804c 0x10>;
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reg-names = "phy";
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#address-cells = <1>;
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#size-cells = <0>;
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sata-phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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sata-phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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};
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18
Documentation/devicetree/bindings/phy/pxa1928-usb-phy.txt
Normal file
18
Documentation/devicetree/bindings/phy/pxa1928-usb-phy.txt
Normal file
@@ -0,0 +1,18 @@
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* Marvell PXA1928 USB and HSIC PHYs
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Required properties:
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- compatible: "marvell,pxa1928-usb-phy" or "marvell,pxa1928-hsic-phy"
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- reg: base address and length of the registers
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- clocks - A single clock. From common clock binding.
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- #phys-cells: should be 0. From commmon phy binding.
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- resets: reference to the reset controller
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Example:
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usbphy: phy@7000 {
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compatible = "marvell,pxa1928-usb-phy";
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reg = <0x7000 0xe0>;
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clocks = <&apmu_clocks PXA1928_CLK_USB>;
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#phy-cells = <0>;
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};
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@@ -6,6 +6,7 @@ This file provides information on what the device node for the R-Car generation
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Required properties:
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- compatible: "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
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"renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
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"renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC.
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- reg: offset and length of the register block.
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- #address-cells: number of address cells for the USB channel subnodes, must
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be <1>.
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@@ -1,5 +1,15 @@
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TWL BCI (Battery Charger Interface)
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The battery charger needs to interact with the USB phy in order
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to know when charging is permissible, and when there is a connection
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or disconnection.
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The choice of phy cannot be configured at a hardware level, so there
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is no value in explicit configuration in device-tree. Rather
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if there is a sibling of the BCI node which is compatible with
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"ti,twl4030-usb", then that is used to determine when and how
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use USB power for charging.
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Required properties:
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- compatible:
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- "ti,twl4030-bci"
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@@ -1,35 +0,0 @@
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* Freescale i.MX ci13xxx usb controllers
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Required properties:
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- compatible: Should be "fsl,imx27-usb"
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- reg: Should contain registers location and length
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- interrupts: Should contain controller interrupt
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- fsl,usbphy: phandle of usb phy that connects to the port
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Recommended properies:
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- phy_type: the type of the phy connected to the core. Should be one
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of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
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property the PORTSC register won't be touched
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- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
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Optional properties:
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- fsl,usbmisc: phandler of non-core register device, with one argument
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that indicate usb controller index
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- vbus-supply: regulator for vbus
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- disable-over-current: disable over current detect
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- external-vbus-divider: enables off-chip resistor divider for Vbus
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- maximum-speed: limit the maximum connection speed to "full-speed".
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- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
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Examples:
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usb@02184000 { /* USB OTG */
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compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
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reg = <0x02184000 0x200>;
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interrupts = <0 43 0x04>;
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fsl,usbphy = <&usbphy1>;
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fsl,usbmisc = <&usbmisc 0>;
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disable-over-current;
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external-vbus-divider;
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maximum-speed = "full-speed";
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tpl-support;
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};
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@@ -1,17 +0,0 @@
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Qualcomm CI13xxx (Chipidea) USB controllers
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Required properties:
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- compatible: should contain "qcom,ci-hdrc"
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- reg: offset and length of the register set in the memory map
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- interrupts: interrupt-specifier for the controller interrupt.
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- usb-phy: phandle for the PHY device
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- dr_mode: Should be "peripheral"
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Examples:
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gadget@f9a55000 {
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compatible = "qcom,ci-hdrc";
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reg = <0xf9a55000 0x400>;
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dr_mode = "peripheral";
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interrupts = <0 134 0>;
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usb-phy = <&usbphy0>;
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};
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@@ -1,15 +1,35 @@
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* USB2 ChipIdea USB controller for ci13xxx
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Required properties:
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- compatible: should be "chipidea,usb2"
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- compatible: should be one of:
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"fsl,imx27-usb"
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"lsi,zevio-usb"
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"qcom,ci-hdrc"
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"chipidea,usb2"
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- reg: base address and length of the registers
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- interrupts: interrupt for the USB controller
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Recommended properies:
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- phy_type: the type of the phy connected to the core. Should be one
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of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
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property the PORTSC register won't be touched.
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- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
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Deprecated properties:
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- usb-phy: phandle for the PHY device. Use "phys" instead.
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- fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead.
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Optional properties:
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- clocks: reference to the USB clock
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- phys: reference to the USB PHY
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- phy-names: should be "usb-phy"
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- vbus-supply: reference to the VBUS regulator
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- maximum-speed: limit the maximum connection speed to "full-speed".
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- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
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- fsl,usbmisc: (FSL only) phandler of non-core register device, with one
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argument that indicate usb controller index
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- disable-over-current: (FSL only) disable over current detect
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- external-vbus-divider: (FSL only) enables off-chip resistor divider for Vbus
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Example:
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@@ -1,17 +0,0 @@
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* LSI Zevio USB OTG Controller
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Required properties:
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- compatible: Should be "lsi,zevio-usb"
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- reg: Should contain registers location and length
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- interrupts: Should contain controller interrupt
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Optional properties:
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- vbus-supply: regulator for vbus
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Examples:
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usb0: usb@b0000000 {
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reg = <0xb0000000 0x1000>;
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compatible = "lsi,zevio-usb";
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interrupts = <8>;
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vbus-supply = <&vbus_reg>;
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};
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@@ -49,8 +49,7 @@ st_dwc3: dwc3@8f94000 {
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st,syscfg = <&syscfg_core>;
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resets = <&powerdown STIH407_USB3_POWERDOWN>,
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<&softreset STIH407_MIPHY2_SOFTRESET>;
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reset-names = "powerdown",
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"softreset";
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reset-names = "powerdown", "softreset";
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#address-cells = <1>;
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#size-cells = <1>;
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pinctrl-names = "default";
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@@ -62,7 +61,7 @@ st_dwc3: dwc3@8f94000 {
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reg = <0x09900000 0x100000>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
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dr_mode = "host";
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phys-names = "usb2-phy", "usb3-phy";
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phys = <&usb2_picophy2>, <&phy_port2 MIPHY_TYPE_USB>;
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phy-names = "usb2-phy", "usb3-phy";
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phys = <&usb2_picophy2>, <&phy_port2 PHY_TYPE_USB3>;
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};
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};
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@@ -38,6 +38,8 @@ Optional properties:
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- snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
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utmi_l1_suspend_n, false when asserts utmi_sleep_n
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- snps,hird-threshold: HIRD threshold
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- snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for
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UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3.
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This is usually a subnode to DWC3 glue to which it is connected.
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@@ -69,6 +69,17 @@ Optional properties:
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(no, min, max) where each value represents either a voltage
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in microvolts or a value corresponding to voltage corner.
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- qcom,manual-pullup: If present, vbus is not routed to USB controller/phy
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and controller driver therefore enables pull-up explicitly
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before starting controller using usbcmd run/stop bit.
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- extcon: phandles to external connector devices. First phandle
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should point to external connector, which provide "USB"
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cable events, the second should point to external connector
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device, which provide "USB-HOST" cable events. If one of
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the external connector devices is not required empty <0>
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phandle should be specified.
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Example HSUSB OTG controller device node:
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usb@f9a55000 {
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@@ -4,6 +4,7 @@ Required properties:
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- compatible: Must contain one of the following:
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- "renesas,usbhs-r8a7790"
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- "renesas,usbhs-r8a7791"
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- "renesas,usbhs-r8a7794"
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- reg: Base address and length of the register for the USBHS
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- interrupts: Interrupt specifier for the USBHS
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- clocks: A list of phandle + clock specifier pairs
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@@ -30,6 +30,9 @@ TWL4030 USB PHY AND COMPARATOR
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- usb_mode : The mode used by the phy to connect to the controller. "1"
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specifies "ULPI" mode and "2" specifies "CEA2011_3PIN" mode.
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If a sibling node is compatible "ti,twl4030-bci", then it will find
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this device and query it for USB power status.
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twl4030-usb {
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compatible = "ti,twl4030-usb";
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interrupts = < 10 4 >;
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@@ -13,6 +13,8 @@ Optional properties:
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- big-endian-desc : boolean, set this for hcds with big-endian descriptors
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- big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
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- needs-reset-on-resume : boolean, set this to force EHCI reset after resume
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- has-transaction-translator : boolean, set this if EHCI have a Transaction
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Translator built into the root hub.
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- clocks : a list of phandle + clock specifier pairs
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- phys : phandle + phy specifier pair
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- phy-names : "usb"
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