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clk: samsung: exynos5433: Add clocks for CMU_DISP domain

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This patch adds the the mux/divider/gate clocks for CMU_DISP domain
which includes clocks of the display IPs (DECON/HDMI/DSIM/MIXER).

Also, CMU_DISP requires 'sclk_hdmi_spdif_disp' source clock from CMU_TOP
domain. This patch adds the clocks of CMU_TOP related to HDMI.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi
2015-02-02 23:24:02 +09:00
committed by Sylwester Nawrocki
parent 06d2f9dfa6
commit 2a1808a6c0
2 changed files with 550 additions and 1 deletions
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114
include/dt-bindings/clock/exynos5433.h
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@@ -68,6 +68,7 @@
#define CLK_MOUT_SCLK_SPDIF 61
#define CLK_MOUT_SCLK_AUDIO1 62
#define CLK_MOUT_SCLK_AUDIO0 63
#define CLK_MOUT_SCLK_HDMI_SPDIF 64
#define CLK_DIV_ACLK_FSYS_200 100
#define CLK_DIV_ACLK_IMEM_SSSX_266 101
@@ -337,8 +338,9 @@
#define CLK_SCLK_BUS_PLL 198
#define CLK_SCLK_BUS_PLL_APOLLO 199
#define CLK_SCLK_BUS_PLL_ATLAS 200
#define CLK_SCLK_HDMI_SPDIF_DISP 201
#define MIF_NR_CLK 201
#define MIF_NR_CLK 202
/* CMU_PERIC */
#define CLK_PCLK_SPI2 1
@@ -514,4 +516,114 @@
#define G2D_NR_CLK 27
/* CMU_DISP */
#define CLK_FOUT_DISP_PLL 1
#define CLK_MOUT_DISP_PLL 2
#define CLK_MOUT_SCLK_DSIM1_USER 3
#define CLK_MOUT_SCLK_DSIM0_USER 4
#define CLK_MOUT_SCLK_DSD_USER 5
#define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6
#define CLK_MOUT_SCLK_DECON_VCLK_USER 7
#define CLK_MOUT_SCLK_DECON_ECLK_USER 8
#define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9
#define CLK_MOUT_ACLK_DISP_333_USER 10
#define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11
#define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12
#define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13
#define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14
#define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15
#define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16
#define CLK_MOUT_SCLK_DSIM0 17
#define CLK_MOUT_SCLK_DECON_TV_ECLK 18
#define CLK_MOUT_SCLK_DECON_VCLK 19
#define CLK_MOUT_SCLK_DECON_ECLK 20
#define CLK_MOUT_SCLK_DSIM1_B_DISP 21
#define CLK_MOUT_SCLK_DSIM1_A_DISP 22
#define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23
#define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24
#define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25
#define CLK_DIV_SCLK_DSIM1_DISP 30
#define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31
#define CLK_DIV_SCLK_DSIM0_DISP 32
#define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33
#define CLK_DIV_SCLK_DECON_VCLK_DISP 34
#define CLK_DIV_SCLK_DECON_ECLK_DISP 35
#define CLK_DIV_PCLK_DISP 36
#define CLK_ACLK_DECON_TV 40
#define CLK_ACLK_DECON 41
#define CLK_ACLK_SMMU_TV1X 42
#define CLK_ACLK_SMMU_TV0X 43
#define CLK_ACLK_SMMU_DECON1X 44
#define CLK_ACLK_SMMU_DECON0X 45
#define CLK_ACLK_BTS_DECON_TV_M3 46
#define CLK_ACLK_BTS_DECON_TV_M2 47
#define CLK_ACLK_BTS_DECON_TV_M1 48
#define CLK_ACLK_BTS_DECON_TV_M0 49
#define CLK_ACLK_BTS_DECON_NM4 50
#define CLK_ACLK_BTS_DECON_NM3 51
#define CLK_ACLK_BTS_DECON_NM2 52
#define CLK_ACLK_BTS_DECON_NM1 53
#define CLK_ACLK_BTS_DECON_NM0 54
#define CLK_ACLK_AHB2APB_DISPSFR2P 55
#define CLK_ACLK_AHB2APB_DISPSFR1P 56
#define CLK_ACLK_AHB2APB_DISPSFR0P 57
#define CLK_ACLK_AHB_DISPH 58
#define CLK_ACLK_XIU_TV1X 59
#define CLK_ACLK_XIU_TV0X 60
#define CLK_ACLK_XIU_DECON1X 61
#define CLK_ACLK_XIU_DECON0X 62
#define CLK_ACLK_XIU_DISP1X 63
#define CLK_ACLK_XIU_DISPNP_100 64
#define CLK_ACLK_DISP1ND_333 65
#define CLK_ACLK_DISP0ND_333 66
#define CLK_PCLK_SMMU_TV1X 67
#define CLK_PCLK_SMMU_TV0X 68
#define CLK_PCLK_SMMU_DECON1X 69
#define CLK_PCLK_SMMU_DECON0X 70
#define CLK_PCLK_BTS_DECON_TV_M3 71
#define CLK_PCLK_BTS_DECON_TV_M2 72
#define CLK_PCLK_BTS_DECON_TV_M1 73
#define CLK_PCLK_BTS_DECON_TV_M0 74
#define CLK_PCLK_BTS_DECONM4 75
#define CLK_PCLK_BTS_DECONM3 76
#define CLK_PCLK_BTS_DECONM2 77
#define CLK_PCLK_BTS_DECONM1 78
#define CLK_PCLK_BTS_DECONM0 79
#define CLK_PCLK_MIC1 80
#define CLK_PCLK_PMU_DISP 81
#define CLK_PCLK_SYSREG_DISP 82
#define CLK_PCLK_HDMIPHY 83
#define CLK_PCLK_HDMI 84
#define CLK_PCLK_MIC0 85
#define CLK_PCLK_DSIM1 86
#define CLK_PCLK_DSIM0 87
#define CLK_PCLK_DECON_TV 88
#define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89
#define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90
#define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91
#define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92
#define CLK_SCLK_DSIM1 93
#define CLK_SCLK_DECON_TV_VCLK 94
#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95
#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96
#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97
#define CLK_PHYCLK_HDMI_PIXEL 98
#define CLK_SCLK_RGB_VCLK_TO_SMIES 99
#define CLK_SCLK_FREQ_DET_DISP_PLL 100
#define CLK_SCLK_RGB_VCLK_TO_DSIM0 101
#define CLK_SCLK_RGB_VCLK_TO_MIC0 102
#define CLK_SCLK_DSD 103
#define CLK_SCLK_HDMI_SPDIF 104
#define CLK_SCLK_DSIM0 105
#define CLK_SCLK_DECON_TV_ECLK 106
#define CLK_SCLK_DECON_VCLK 107
#define CLK_SCLK_DECON_ECLK 108
#define CLK_SCLK_RGB_VCLK 109
#define CLK_SCLK_RGB_TV_VCLK 110
#define DISP_NR_CLK 111
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */