xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+

Browse Source 
On B0 and C0 steppings the workaround enable bit would be overriden by
default, so the overriding must be disabled.

The WA was added in
commit 83a24979c4
Author: Nick Hoath <nicholas.hoath@intel.com>
Date:   Fri Apr 10 13:12:26 2015 +0100

    drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent

Spotted-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Imre Deak
2015-05-19 17:05:41 +03:00
committed by Daniel Vetter
parent 118182e9d7
commit 2a0ee94fef
2 changed files with 6 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/drm/i915/intel_ringbuffer.c
View File

@@ -1043,6 +1043,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
{
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t tmp;
gen9_init_workarounds(ring);
@@ -1058,8 +1059,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
}
/* WaForceContextSaveRestoreNonCoherent:bxt */
WA_SET_BIT_MASKED(HDC_CHICKEN0,
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
if (INTEL_REVID(dev) >= BXT_REVID_B0)
tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
return 0;
}