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crypto: chelsio - Remove allocation of sg list to implement 2K limit of dsgl header

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Update DMA address index instead of allocating new sg list to impose  2k size limit for each entry.

Signed-off-by: Harsh Jain <harsh@chelsio.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Harsh Jain
2017-10-08 13:37:22 +05:30
committed by Herbert Xu
parent de1a00ac7d
commit 2956f36c95
4 changed files with 76 additions and 172 deletions
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3
drivers/crypto/chelsio/chcr_algo.h
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@@ -221,7 +221,7 @@
#define MAX_WR_SIZE 512
#define ROUND_16(bytes) ((bytes) & 0xFFFFFFF0)
#define MAX_DSGL_ENT 32
#define MAX_DIGEST_SKB_SGE (MAX_SKB_FRAGS - 2)
#define MAX_DIGEST_SKB_SGE (MAX_SKB_FRAGS - 1)
#define MIN_CIPHER_SG 1 /* IV */
#define MIN_AUTH_SG 2 /*IV + AAD*/
#define MIN_GCM_SG 2 /* IV + AAD*/
@@ -261,7 +261,6 @@ struct cipher_wr_param {
struct scatterlist *srcsg;
char *iv;
int bytes;
short int snent;
unsigned short qid;
};
enum {